参数资料
型号: PE33361MLIAA-Z
厂商: PEREGRINE SEMICONDUCTOR CORP
元件分类: PLL合成/DDS/VCOs
英文描述: PHASE LOCKED LOOP, QCC48
封装: 7 X 7 MM, GREEN, QFN-48
文件页数: 14/15页
文件大小: 344K
代理商: PE33361MLIAA-Z
Advance Information
PE33361
Page 8 of 15
2009 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0287-01
│ UltraCMOS RFIC Solutions
Functional Description
The PE33361 consists of a prescaler, counters, a
phase detector, and control logic. The dual
modulus prescaler divides the VCO frequency by
either 10 or 11, depending on the value of the
modulus select. Counters “R” and “M” divide the
reference and prescaler output, respectively, by
integer values stored in a 20-bit register. An
additional counter (“A”) is used in the modulus
select logic. The phase-frequency detector
generates up and down frequency control signals.
The control logic includes a selectable chip
interface. Data can be written via serial bus,
parallel bus, or hardwired directly to the pins.
There are also various operational and test modes
and a lock detect output.
Figure 6. Functional Block Diagram
Control
Logic
R Counter
(6-bit)
Phase
Detector
fc
PD_U
PD_D
LD
R(5:0)
M(8:0)
A(3:0)
D(7:0)
Sdata
Control
Pins
fr
Modulus
Select
10/11
Prescaler
M Counter
(9-bit)
Cext
fp
Fin
FINB
PD_DB
PD_UB
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