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参数资料
| 型号： | PE33361MLIAA-Z |
| 厂商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, QCC48 |
| 封装： | 7 X 7 MM, GREEN, QFN-48 |
| 文件页数： | 4/15页 |
| 文件大小： | 344K |
| 代理商： | PE33361MLIAA-Z |
Advance Information
PE33361
Page 12 of 15
2009 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0287-01
│ UltraCMOS RFIC Solutions
voltage. PD_UB pulses result in an increase in
VCO frequency and PD_DB results in a decrease
in VCO frequency.
A lock detect output, LD is also provided, via the
pin Cext. Cext is the logical “NAND” of PD_
UB
and PD_DB waveforms, which is driven through a
series 2k ohm resistor. Connecting Cext to an
external shunt capacitor provides integration.
Cext also drives the input of an internal inverting
comparator with an open drain output. Thus LD is
an “AND” function of PD_
UB and PD_DB. See
Figure 6 for a functional block diagram of this
circuit.
Enhancement Register
The functions of the enhancement register bits are shown below with all bits active “high”.
Table 9. Enhancement Register Bit Functionality
** Program to 0
Phase Detector
The phase detector is triggered by rising edges
from the main Counter (fp) and the reference
counter (fc). It has two outputs, namely PD_UB,
and PD_DB . If the divided VCO leads the divided
reference in phase or frequency (fp leads fc),
PD_DB pulses “low”. If the divided reference
leads the divided VCO in phase or frequency (fr
leads fp), PD_UB pulses “low”. The width of either
pulse is directly proportional to phase offset
between the two input signals, fp and fc. The
phase detector gain is 430 mV / radian.
PD_
UB and PD_DB are designed to drive an
active loop filter which controls the VCO tune
Bit Function
Description
Bit 0
Reserved**
Bit 1
Reserved**
Bit 2
Reserved**
Bit 3
Power down
Power down of all functions except programming interface.
Bit 4
Counter load
Immediate and continuous load of counter programming as directed by the
BmodeB and
Smode inputs.
Bit 5
MSEL output
Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.
Bit 6
Prescaler output
Drives the raw internal prescaler output (fmain) onto the Dout output.
Bit 7
fp, fc OE
fp, fc outputs disabled.
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