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参数资料
| 型号： | PE33361MLIAA-Z |
| 厂商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, QCC48 |
| 封装： | 7 X 7 MM, GREEN, QFN-48 |
| 文件页数： | 9/15页 |
| 文件大小： | 344K |
| 代理商： | PE33361MLIAA-Z |
Advance Information
PE33361
Page 3 of 15
Document No. 70-0287-01
│ www.psemi.com
2009 Peregrine Semiconductor Corp. All rights reserved.
Table 1. Pin Descriptions (continued)
Pin No.
Pin Name
Interface Mode
Type
Description
9
Sclk
Serial
Input
Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR
“low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk.
D6
Parallel
Input
Parallel data bus bit6.
M6
Direct
Input
M Counter bit6.
10
FSELS
Serial
Input
Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for
programming of internal counters while in Serial Interface Mode.
D7
Parallel
Input
Parallel data bus bit7 (MSB).
Pre_enB
Direct
Input
Prescaler enable, active “low”. When “high”, Fin bypasses the prescaler.
11
GND
ALL
Ground.
12
FSELP
Parallel
Input
Selects contents of primary register (FSELP=1) or secondary register (FSELP=0) for
programming of internal counters while in Parallel Interface Mode.
A0
Direct
Input
A Counter bit0 (LSB).
13
E_WR
Serial
Input
Enhancement register write enable. While E_WR is “high”, Sdata can be serially
clocked into the enhancement register on the rising edge of Sclk.
Parallel
Input
Enhancement register write. D[7:0] are latched into the enhancement register on the
rising edge of E_WR.
A1
Direct
Input
A Counter bit1.
14
M2_WR
Parallel
Input
M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the rising
edge of M2_WR.
A2
Direct
Input
A Counter bit2.
15
Smode
Serial, Parallel
Input
Selects serial bus interface mode (BmodeB=0, Smode=1) or Parallel Interface Mode
(BmodeB=0, Smode=0).
A3
Direct
Input
A Counter bit3 (MSB).
16
BmodeB
ALL
Input
Selects direct interface mode (BmodeB=1).
17
VDD
ALL
(Note 1)
Power supply input. Input may range from 2.85 V to 3.45 V. Bypassing
recommended.
18
VDD
ALL
(Note 1)
Power supply input. Input may range from 2.85 V to 3.45 V. Bypassing
recommended.
19
M1_WR
Parallel
Input
M1 write. D[7:0] are latched into the primary register (Pre_enB, M[6:0]) on the rising
edge of M1_WR.
20
A_WR
Parallel
Input
A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the rising edge
of A_WR.
21
Hop_WR
Serial, Parallel
Input
Hop write. The contents of the primary register are latched into the secondary
register on the rising edge of Hop_WR.
22
Fin
ALL
Input
Prescaler input from the VCO. 3.5 GHz max frequency.
23
FinB
ALL
Input
Prescaler complementary input. A bypass capacitor in series with a 51
resistor
should be placed as close as possible to this pin and be connected directly to the
ground plane.
24
GND
ALL
Ground.
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