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参数资料
| 型号： | PE33361MLIAA-Z |
| 厂商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, QCC48 |
| 封装： | 7 X 7 MM, GREEN, QFN-48 |
| 文件页数： | 15/15页 |
| 文件大小： | 344K |
| 代理商： | PE33361MLIAA-Z |
Advance Information
PE33361
Page 9 of 15
Document No. 70-0287-01
│ www.psemi.com
2009 Peregrine Semiconductor Corp. All rights reserved.
Main Counter Chain
Normal Operating Mode
The main counter chain divides the RF input
frequency, Fin, by an integer derived from the
user-defined values in the “M” and “A” counters. It
is composed of the 10/11 dual modulus prescaler,
modulus select logic, and 9-bit M counter. Setting
Pre_enB “low” enables the 10/11 prescaler.
Setting Pre_enB “high” allows Fin to bypass the
prescaler and powers down the prescaler.
The output from the main counter chain, fp, is
related to the VCO frequency, Fin, by the following
equation:
fp = Fin / [10 x (M + 1) + A]
(1)
where A
≤ M + 1, 1 ≤ M ≤ 511
When the loop is locked, Fin is related to the
reference frequency, fr, by the following equation:
Fin = [10 x (M + 1) + A] x (fr / (R+1))
(2)
where A
≤ M + 1, 1 ≤ M ≤ 511
A consequence of the upper limit on A is that Fin
must be greater than or equal to 90 x (fr / (R+1)) to
obtain contiguous channels. Programming the M
Counter with the minimum value of “1” will result in
a minimum M Counter divide ratio of “2”.
In Direct Interface Mode, main counter inputs M7
and M8 are internally forced low. In this mode, the
M value is limited to 1
≤ M ≤ 127.
Prescaler Bypass Mode
Setting Pre_enB “high” allows Fin to bypass and
power down the prescaler. In this mode, the
10/11 prescaler and A register are not active, and
the input VCO frequency is divided by the M
counter directly. The following equation relates Fin
to the reference frequency, fr:
Fin = (M + 1) x (fr / (R+1)) )
(3)
where 1 ≤ M ≤ 511
In Direct Interface Mode, main counter inputs M7
and M8 are internally forced low. In this mode, the
M value is limited to 1
≤ M ≤ 127.
Reference Counter
The reference counter chain divides the
reference frequency, fr, down to the phase
detector comparison frequency, fc.
The output frequency of the 6-bit R Counter is
related to the reference frequency by the
following equation:
fc = fr / (R + 1)
(4)
where 0 ≤ R ≤ 63
Note that programming R with “0” will pass the
reference frequency, fr, directly to the phase
detector.
In Direct Interface Mode, R Counter inputs R4
and R5 are internally forced low (“0”).
In this
mode, the R value is limited to 0
≤ R ≤ 15.
Register Programming
Parallel Interface Mode
Parallel Interface Mode is selected by setting the
BmodeB input “low” and the Smode input “low”.
Parallel input data, D[7:0], are latched in a
parallel fashion into one of three 8-bit primary
register sections on the rising edge of M1_WR,
M2_WR, or A_WR per the mapping shown in
Table 7 on page 10.
The contents of the
primary register are transferred into a secondary
register
on
the
rising
edge
of
Hop_WR
according to the timing diagram shown in Figure
7. Data is transferred to the counters as shown
in Table 7 on page 10.
The secondary register acts as a buffer to allow
rapid
changes to the VCO frequency.
This
double buffering for “ping-pong” counter control
is programmed via the FSELP input.
When
FSELP is “high”, the primary register contents
set the counter inputs. When FSELP is “low”,
the secondary register contents are utilized.
Parallel input data, D[7:0], are latched into the
enhancement register on the rising edge of
E_WR according to the timing diagram shown in
Figure 7. This data provides control bits as
shown in Table 8 on page 10 with bit
functionality enabled by asserting the EnhB
input “low”.
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