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| 型号： | PEF20324 |
| 厂商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | ICs for Communications |
| 中文描述： | 通信集成电路 |
| 文件页数： | 21/63页 |
| 文件大小： | 705K |
| 代理商： | PEF20324 |
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PEB 20324
PEF 20324
Pin Descriptions
Hardware Reference Manual
21
04.99
Table 2-5
Pin No.
2, 5…8,
11…13, 30,
33…36,
39…41,
45…48,
51…54,
148, 149,
152…156,
159
Pin Descriptions by Functional Block: PCI Interface
Symbol
Type Description
AD(31:0)
t/s
Address/Data Bus
A bus transaction consists of an address phase
followed by one or more data phases.
When MUNICH128X is Master, AD(31:0) are outputs
in the address phase of a transaction. During the data
phases, AD(31:0) remain outputs for write
transactions, and become inputs for read
transactions.
When MUNICH128X is Slave, AD(31:0) are inputs in
the address phase of a transaction. During the data
phases, AD(31:0) remain inputs for write transactions,
and become outputs for read transactions.
AD(31:0) is sampled on the rising edge of CLK.
C/BE(3:0)
t/s
Command/Byte Enable
During the address phase of a transaction, C/BE(3:0)
define the bus command. During the data phase, C/
BE(3:0) are used as Byte Enables. The Byte Enables
are valid for the entire data phase and determine
which byte lanes carry meaningful data. C/BE0
applies to byte 0 (lsb) and C/BE3 applies to byte 3
(msb).
When MUNICH128X is Master, C/BE(3:0) are
outputs.
When MUNICH128X is Slave, C/BE(3:0) are inputs.
C/BE(3:0) is sampled on the rising edge of CLK.
PAR
t/s
Parity
PAR is even parity across AD(31:0) and C/BE(3:0).
PAR is stable and valid one clock after the address
phase. PAR has the same timing as AD(31:0) but
delayed by one clock.
When MUNICH128X is Master, PAR is output during
address phase and write data phases.
When MUNICH128X is Slave, PAR is output during
read data phases. Parity errors detected by the
MUNICH128X are indicated on PERR output. PAR is
sampled on the rising edge of CLK.
14, 29, 42,
160
28
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