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| 型号： | PEF20324 |
| 厂商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | ICs for Communications |
| 中文描述： | 通信集成电路 |
| 文件页数： | 57/63页 |
| 文件大小： | 705K |
| 代理商： | PEF20324 |
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PEB 20324
PEF 20324
Test Modes
Hardware Reference Manual
57
04.99
6
Test Modes
6.1
Boundary Scan Unit
In the MUNICH128X a Test Access Port (TAP) controller is implemented. The essential
part of the TAP is a finite state machine (16 states) controlling the different operational
modes of the boundary scan. Both, TAP controller and boundary scan, meet the
requirements given by the JTAG standard: IEEE 1149.1.
Figure 6-1
gives an overview.
Figure 6-1
Block Diagram of Test Access Port and Boundary Scan
If no boundary scan operation is planned TRST has to be connected with V
SS
. TMS and
TDI do not need to be connected since pull-up transistors ensure high input levels in this
case. Nevertheless it would be a good practice to put the unused inputs to defined levels.
In this case, if the JTAG is not used:
TMS = TCK = ’1’ is recommended.
Test handling (boundary scan operation) is performed via the pins TCK (Test Clock),
TMS (Test Mode Select), TDI (Test Data Input) and TDO (Test Data Output) when the
TAP controller is not in its reset state, i.e. TRST is connected to V
DD
or it remains
unconnected due to its internal pull-up. Test data at TDI are loaded with a 4-MHz clock
Clock Generation
Test Access Port
TAP Controller
- Finite State Machine
- Instruction Register (3 bit)
- Test Signal Generator
CLOCK
TCK
TRST
TMS
Reset
Data in
TDI
Test
Control
TDO
Enable
Data out
CLOCK
B
I
B
6
Control
Bus
ID Data out
SS Data
out
n
.
.
.
.
.
.
1
2
Pins
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