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| 型号： | PEF20324 |
| 厂商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | ICs for Communications |
| 中文描述： | 通信集成电路 |
| 文件页数： | 47/63页 |
| 文件大小： | 705K |
| 代理商： | PEF20324 |
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PEB 20324
PEF 20324
Electrical Characteristics
Hardware Reference Manual
47
04.99
5.7.1.2
The transaction starts when FRAME is activated (clock 2 in
figure 5-5
). A write
transaction is similar to a read transaction except no turnaround cycle is required
following the address phase. In the example, the first and second data phases complete
with zero wait cycles. The third data phase has three wait cycles inserted by the target.
Both initiator and target insert a wait cycle on clock 5. In the case where the initiator
inserts a wait cycle (clock 5), the data is held on the bus, but the byte enables are
withdrawn. The last data phase is characterized by IRDY being asserted while the
FRAME signal is deasserted. This data phase is completed when TRDY goes active
(clock 8).
PCI Write Transaction
Figure 5-5
PCI Write Transaction
ITD07576
Address
1
2
3
4
5
6
7
8
9
Bus CMD
W
CLK
FRAME
AD
C/BE
IRDY
TRDY
DEVSEL
Address
Phase
Data
Phase
Bus Transaction
BE’s-1
D
D
D
W
W
Data 1
Data 2
Data 3
BE’s-2
BE’s-3
Phase
Data
Data
Phase
相关PDF资料 |
PDF描述 |
|---|---|
| PEB20324 | ICs for Communications |
| PEF20532 | 2 Channel Serial Optimized Communication Controller |
| PEB20532 | 2 Channel Serial Optimized Communication Controller |
| PEF20534 | DMA Supported Serial Communication Controller with 4 Channels |
| PEB20534 | DMA Supported Serial Communication Controller with 4 Channels |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PEF20324HV2.2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PEF2035NV4.1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PEF2035NV4.1ACFA | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PEF2035NV4.1-ACFA | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PEF2041N | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Telecom Switching Circuit |
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