参数资料
型号: PEF20324
厂商: INFINEON TECHNOLOGIES AG
英文描述: ICs for Communications
中文描述: 通信集成电路
文件页数: 29/63页
文件大小: 705K
代理商: PEF20324
PEB 20324
PEF 20324
Functional Description
Hardware Reference Manual
29
04.99
3.3
Functional Blocks
Each core consists of dedicated circuitry: Serial PCM Interface Controller, Configuration
and State RAM (CSR), 24/32-channel HDLC Controller with internal Transmit and
Receive Buffers, 64-Channel DMA Controller, and Register Set.
3.3.1
This block controls both Parallel–to-Serial (Tx) and Serial-to-Parallel (Rx) conversion
and PCM timing. Additionally, this block controls the multiplexing of channels through the
HDLC controller, as well as switching for the test loops.
Serial PCM Interface Controller
3.3.2
This block contains internal RAM which maintains the state of each channel. The
Multiplex Control Block of the Serial PCM Interface Controller handles the switching of
the CSR information into and out of the 24/32-channel HDLC Controller.
Configuration and State RAM (CSR)
3.3.3
The HDLC Controller performs protocol processing for each channel independently,
based on the CSR information for each channel.
24/32-channel HDLC Controller
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