参数资料
型号: PEF20324
厂商: INFINEON TECHNOLOGIES AG
英文描述: ICs for Communications
中文描述: 通信集成电路
文件页数: 27/63页
文件大小: 705K
代理商: PEF20324
PEB 20324
PEF 20324
Pin Descriptions
Hardware Reference Manual
27
04.99
Table 2-8
Pin No.
115
Pin Descriptions by Functional Block: Test Interface
Symbol
Type Description
TCK
I
JTAG Test Clock
A Pull-Up resistor to V
DD3
is recommended if
boundary scan unit is not used.
TMS
I
JTAG Test Mode Select
A Pull-Up resistor to V
DD3
is recommended if
boundary scan unit is not used.
TDI
I
JTAG Test Data Input
A Pull-Up resistor to V
DD3
is recommended if
boundary scan unit is not used.
TDO
O
JTAG Test Data Output
TRST
I
JTAG Reset
TRST should be connected to VSS if boundary
scan unit is not used.
116
121
120
119
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