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| 型号： | PEF20324 |
| 厂商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | ICs for Communications |
| 中文描述： | 通信集成电路 |
| 文件页数： | 62/63页 |
| 文件大小： | 705K |
| 代理商： | PEF20324 |
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PEB 20324
PEF 20324
Test Modes
Hardware Reference Manual
62
04.99
The desired test mode is selected by serially loading a 3-bit instruction code into the
instruction register via TDI (LSB first); see
Table 6-2.
Table 6-2
Boundary Scan Test Modes
Instruction (Bit 2 … 0)
Test Mode
000
001
010
011
111
others
handled like BYPASS
EXTEST
is used to examine the interconnection of the devices on the board. In this test
mode at first all input pins
capture
the current level on the corresponding external
interconnection line, whereas all output pins are held at constant values (‘0’ or ‘1’,
according to
Table 6-1
). Then the contents of the boundary scan is
shifted
to TDO. At
the same time the next scan vector is loaded from TDI. Subsequently all output pins are
updated
according to the new boundary scan contents and all input pins again capture
the current external level afterwards, and so on.
INTEST
supports internal testing of the chip, i.e. the output pins
capture
the current level
on the corresponding internal line whereas all input pins are held on constant values (‘0’
or ‘1’, according to
Table 6-1
). The resulting boundary scan vector is
shifted
to TDO.
The next test vector is serially loaded via TDI. Then all input pins are
updated
for the
following test cycle.
Note:
In capture IR-state the code ‘001’ is automatically loaded into the instruction
register, i.e. if INTEST is wanted the shift IR-state does not need to be passed.
SAMPLE/PRELOAD
is a test mode which provides a snap-shot of pin levels during
normal operation.
IDCODE
: A 32-bit identification register is serially read out via TDO. It contains the
version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits).
The LSB is fixed to ‘1’.
Note:
Since in test logic reset state the code ‘011’ is automatically loaded into the
instruction register, the ID code can easily be read out in shift DR state which is
reached by TMS = 0, 1, 0, 0.
BYPASS
: A bit entering TDI is shifted to TDO after one TCK clock cycle.
EXTEST (external testing)
INTEST (internal testing)
SAMPLE/PRELOAD (snap-shot testing)
IDCODE (reading ID code)
BYPASS (bypass operation)
TDI ->
0011
0000 0000 0100 0100
0000 1000 001
1
-> TDO
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|---|---|
| PEB20324 | ICs for Communications |
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|---|---|
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