Bipolar Input to Single-Supply Scaling
R =
A
2
R
g
B
1
g
-
9.23077k
=
W
2
10k
0.315789474
W
1
0.315789474
-
R =
X
R
B
A
R +R
B
A
4.81k
=
W
10k
9.23077k
W
W
10k
+9.23077k
W
R
10kW
B
+
R
X
4.81kW
R
A
9.2kW
CH1Input
(2.447817V,
0.0474093V)
V
IN1
(+5V, 5V)
-
V
REF_ADC
(2.5V)
APPLICATIONS: HIGH GAIN/WIDE
k
=k
k
0.96=0.98
0.02
-
VO
VO+
VO
-
g=
k
V
VO
REF_ADC
2
|V |
k
-
V
REF_ADC
IN1
VO
0.315789474=
0.96
2.5
2
5
0.96
2.5
-
SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................ www.ti.com
Note that this process assumes a symmetrical VIN1
and that symmetrical scaling is used for CH1 input
minimum and maximum values. The following steps
give the algorithm to compute resistor values for
d. RX can now be computed from the starting value
of RB and the computed value for RA.
Step 1: Choose the following:
a. VREF_ADC = 2.5V (ADC reference voltage)
b. | VIN1 | = 5
(magnitude of VIN, assuming scaling is for ±VIN1)
c. Choose RB as a standard resistor value. The
input on-channel current multiplied by RB should
be less than the input offset voltage, such that RB
is not a major source of inaccuracy.
RB = 10k (select as a starting value for
resistors)
d. For
the
most
negative
VIN1,
choose
the
percentage
(in
decimal
format)
of
VREF_ADC
desired at the ADC input.
kVO– = 0.02
(CH1 input = kVO– × VREF_ADC when VIN1 = –VIN1)
e. For the most positive VIN1, choose the percentage
Figure 78. Bipolar to Single-Ended Input
Algorithm
(in decimal format) of VREF_ADC desired at the
ADC input. Since this scaling is based on
symmetry, kVO+ must be the same percentage
away from VREF_ADC at the upper limit as at the
BANDWIDTH CONSIDERATIONS
lower limit where kVO– is computed.
As a result of the combination of wide bandwidth and
kVO+ = 1 – kVO–
high gain capability of the PGA112/PGA113 and
PGA116/PGA117, there are several printed circuit
kVO+ = 1 – 0.02 = 0.98
board (PCB) design and system recommendations to
consider for optimum application performance.
(CH1 input = kVO+ × VREF_ADC when VIN1 = +VIN1)
1. Power-supply
bypass.
Bypass
each
Step 2: Compute the following:
power-supply pin separately. Use a ceramic
a. To simplify analysis, create one constant called
capacitor
connected
directly
from
the
kVO.
power-supply pin to the ground pin of the IC on
the same PCB plane. Vias can then be used to
connect to ground and voltage planes. This
configuration keeps parasitic inductive paths out
b. A constant, g, is created to simplify resistor value
of the local bypass for the PGA. Good analog
computations.
design practice dictates the use of a large value
tantalum bypass capacitor on the PCB for each
respective voltage.
c. RA is now selected from the starting value of RB
and the g constant.
38
Copyright 2008, Texas Instruments Incorporated