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参数资料
| 型号： | PGA117AIPW |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO20 |
| 封装： | GREEN, PLASTIC, TSSOP-20 |
| 文件页数： | 35/47页 |
| 文件大小： | 1545K |
| 代理商： | PGA117AIPW |
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POWER SUPPLIES
SHUTDOWN AND POWER-ON-RESET (POR)
10kW
ADC
G=1
R
F
R
I
Output
Stage
SPI
Interface
SCLK
DIO
CS
7
V
OUT
5
DV
DD
10
AV
DD
1
GND
6
V
REF
4
3
8
9
MSP430
Microcontroller
+3V
+5V
V
REF
PGA112
PGA113
(MSOP-10)
V
CAL/CH0
2
CH1
CAL3
CAL4
CAL1
CAL2
0.1V
CAL
0.9V
CAL
10kW
80kW
MUX
CAL2/3
SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................ www.ti.com
At initial power-on, the state of the PGA is G = 1 and
Channel 0 active. CAUTION: For most applications,
Figure 80 shows a typical mixed-supply voltage
set AVDD ≥ DVDD to prevent VOUT from driving
system where the analog supply, AVDD, is +5V and
current into AVDD and raising the voltage level of
the digital supply voltage, DVDD, is +3V. The analog
AVDD.
output stage of the PGA and the SPI interface digital
circuitry
are
both
powered
from
DVDD. When
considering the power required for DVDD, use the
Electrical Characteristics table and add any load
The PGA112/PGA113 have a software shutdown
current anticipated on VOUT; this load current must be
mode,
and
the
PGA116/PGA117
offer
both
a
provided by DVDD. This split-supply architecture
hardware and software shutdown mode. When the
ensures
compatible
logic
levels
with
the
PGA is shut down, it goes into a low-power standby
microcontroller. It also ensures that the PGA output
mode. The Electrical Characteristics table details the
cannot run the input for the onboard ADC into an
current draw in shutdown mode with and without the
overvoltage condition; this condition could cause
SPI interface being clocked. In shutdown mode, RF
device latch-up and system lock-up, and require
and RI remain connected between VOUT and VREF.
power-supply sequencing. Each supply pin should be
When DVDD is less than 1.6V, the digital interface is
individually bypassed with a 0.1
F ceramic capacitor
disabled and the channel and gain selections are
directly at the device to ground. If there is only one
held to the respective POR states of Gain = 1 and
power supply in the system, AVDD and DVDD can both
Channel = VCAL/CH0. When DVDD is above 1.8V, the
be connected to the same supply; however, it is
digital interface is enabled and the POR gain and
recommended to use individual bypass capacitors
channel states remain unchanged until a valid SPI
directly at each respective supply pin to a single point
communication is received.
ground. VOUT is diode-clamped to AVDD (as shown in
AVDD + 0.3V. DVDD and AVDD must be within the
operating voltage range of +2.2V to +5.5V.
Figure 80. Split Power-Supply Architecture: AVDD ≠ DVDD
40
Copyright 2008, Texas Instruments Incorporated
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| PGA117AIPWG4 | 功能描述:特殊用途放大器 Programmable Gain Amp w/Mux RoHS:否 制造商:Texas Instruments 通道数量:Single 共模抑制比（最小值）: 输入补偿电压: 工作电源电压:3 V to 5.5 V 电源电流:5 mA 最大功率耗散: 最大工作温度:+ 70 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:QFN-20 封装:Reel |
| PGA117AIPWR | 功能描述:特殊用途放大器 Zero-Drift Program Gain AMP/MUX RoHS:否 制造商:Texas Instruments 通道数量:Single 共模抑制比（最小值）: 输入补偿电压: 工作电源电压:3 V to 5.5 V 电源电流:5 mA 最大功率耗散: 最大工作温度:+ 70 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:QFN-20 封装:Reel |
| PGA117AIPWRG4 | 功能描述:特殊用途放大器 Programmable Gain Amp w/Mux RoHS:否 制造商:Texas Instruments 通道数量:Single 共模抑制比（最小值）: 输入补偿电压: 工作电源电压:3 V to 5.5 V 电源电流:5 mA 最大功率耗散: 最大工作温度:+ 70 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:QFN-20 封装:Reel |
| PGA-120-AH3-S-TG | 制造商:3M Electronic Products Division 功能描述: |
| PGA120M004B1-1315BLU | 制造商:FCI 功能描述: |
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