参数资料
型号: PGA117AIPW
厂商: TEXAS INSTRUMENTS INC
元件分类: 模拟信号调理
英文描述: SPECIALTY ANALOG CIRCUIT, PDSO20
封装: GREEN, PLASTIC, TSSOP-20
文件页数: 44/47页
文件大小: 1545K
代理商: PGA117AIPW
SPI TIMING: VS = AVDD = DVDD = +2.2V to +5V
SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................ www.ti.com
Boldface limits apply over the specified temperature range, TA = –40°C to +125°C.
At TA = +25°C, RL = 10k//CL = 100pF connected to DVDD/2, and VREF = GND, unless otherwise noted.
PGA112, PGA113,
PGA116, PGA117
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input Capacitance (SCLK, CS, and DIO pins)
1
pF
Input Rise/Fall Time(1)
tRFI
2
s
(CS, SCLK, and DIO pins)
Output Rise/Fall Time (DIO pin)(1)
tRFO
CLOAD = 60pF
10
ns
CS High Time (CS pin)(1)
tCSH
40
ns
SCLK Edge to CS Fall Setup Time(1)
tCSO
10
ns
CS Fall to First SCLK Edge Setup Time
tCSSC
10
ns
SCLK Frequency(2)
fSCLK
10
MHz
SCLK High Time(3)
tHI
40
ns
SCLK Low Time(3)
tLO
40
ns
SCLK Last Edge to CS Rise Setup Time(1)
tSCCS
10
ns
CS Rise to SCLK Edge Setup Time(1)
tCS1
10
ns
DIN Setup Time
tSU
10
ns
DIN Hold Time
tHD
10
ns
SCLK to DOUT Valid Propagation Delay(1)
tDO
25
ns
CS Rise to DOUT Forced to Hi-Z(1)
tSOZ
20
ns
(1)
Ensured by design; not production tested.
(2)
When using devices in daisy-chain mode, the maximum clock frequency for SCLK is limited by SCLK rise/fall time, DIN setup time, and
DOUT propagation delay. See Figure 63. Based on this limitation, the maximum SCLK frequency for daisy-chain mode is 9.09MHz.
(3)
tHI and tLO must not be less than 1/SCLK (max).
6
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): PGA112 PGA113 PGA116 PGA117
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