参数资料
型号: PIC12F1840T-I/MF
厂商: Microchip Technology
文件页数: 25/122页
文件大小: 0K
描述: MCU 7KB FLASH 256B RAM XLP 8DFN
标准包装: 3,300
系列: PIC® XLP™ 12F
核心处理器: PIC
芯体尺寸: 8-位
速度: 32MHz
连通性: I²C,LIN,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 5
程序存储器容量: 7KB(4K x 14)
程序存储器类型: 闪存
EEPROM 大小: 256 x 8
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 2.3 V ~ 5.5 V
数据转换器: A/D 4x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 8-VDFN 裸露焊盘
包装: 带卷 (TR)
PIC12(L)F1840
DS41441B-page 120
Preliminary
2011 Microchip Technology Inc.
REGISTER 13-1:
IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER
U-0
R/W-0/0
IOCAP5
IOCAP4
IOCAP3
IOCAP2
IOCAP1
IOCAP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented:
Read as ‘0’
bit 5-0
IOCAP<5:0>:
Interrupt-on-Change PORTA Positive Edge Enable bits
1
= Interrupt-on-Change enabled on the pin for a positive going edge. Associated Status bit and interrupt
flag will be set upon detecting an edge.
0
= Interrupt-on-Change disabled for the associated pin.
REGISTER 13-2:
IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTER
U-0
R/W-0/0
IOCAN5
IOCAN4
IOCAN3
IOCAN2
IOCAN1
IOCAN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented:
Read as ‘0’
bit 5-0
IOCAN<5:0>:
Interrupt-on-Change PORTA Negative Edge Enable bits
1
= Interrupt-on-Change enabled on the pin for a negative going edge. Associated Status bit and interrupt
flag will be set upon detecting an edge.
0
= Interrupt-on-Change disabled for the associated pin.
REGISTER 13-3:
IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER
U-0
R/W/HS-0/0
IOCAF5
IOCAF4
IOCAF3
IOCAF2
IOCAF1
IOCAF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HS - Bit is set in hardware
bit 7-6
Unimplemented:
Read as ‘0’
bit 5-0
IOCAF<5:0>:
Interrupt-on-Change PORTA Flag bits
1
= An enabled change was detected on the associated pin.
Set when IOCAPx = 1 and a rising edge was detected on RAx, or when IOCANx = 1 and a falling edge
was detected on RAx.
0
= No change was detected, or the user cleared the detected change.
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