参数资料
型号: PIC16LC642-04/SP
厂商: Microchip Technology
文件页数: 54/125页
文件大小: 0K
描述: IC MCU OTP 4KX14 COMP 28DIP
产品培训模块: Asynchronous Stimulus
标准包装: 15
系列: PIC® 16C
核心处理器: PIC
芯体尺寸: 8-位
速度: 4MHz
外围设备: 欠压检测/复位,LED,POR,WDT
输入/输出数: 22
程序存储器容量: 7KB(4K x 14)
程序存储器类型: OTP
RAM 容量: 176 x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 6 V
振荡器型: 外部
工作温度: 0°C ~ 70°C
封装/外壳: 28-DIP(0.300",7.62mm)
包装: 管件
Micrel, Inc.
KSZ8862-16/32MQL
April 2007
34
M9999-040407-3.0
Table 2 describes the BIU signal grouping.
Signal
Type
(1)
Function
Common Signals
A[15:1]
I
Address
AEN
I
Address Enable
Address Enable asserted indicates memory address on the bus for DMA access and since
the device is an I/O device, address decoding is only enabled when AEN is low.
BE3N, BE2N,
BE1N, BE0N
I
Byte Enable
BE0N
BE1N
BE2N
BE3N
Description
0
32-bit access (32-bit bus only)
0
1
Lower 16-bit (D[15:0]) access
1
0
Higher 16-bit (D[31:16]) access (32-
bit bus only)
0
1
Byte 0 (D[7:0]) access
1
0
1
Byte 1 (D[15:8]) access
1
0
1
Byte 2 (D[23:16]) access (32-bit bus
only)
1
0
Byte 3 (D[31:24]) access (32-bit bus
only)
Note 1: BE3N, BE2N, BE1N and BE0N are ignored when DATACSN is low because 32 bit
transfers are assumed.
Note 2: BE2N and BE3N are valid only for the KSZ8862-32 mode, and are NC for the
KSZ8862-16 mode.
D[31:16]
I/O
Data
For KSZ8862-32 Mode only
D[15:0]
I/O
Data
For both KSZ8862-32 and KSZ8862-16 Modes
ADSN
I
Address Strobe
The rising edge of ADSN is used to latch A[15:1], AEN, BE3N, BE2N, BE1N and BE0N.
LDEVN
O
Local Device
This signal is a combinatorial decode of AEN and A[15:4], The A[15:4] is used to compare
against the Base Address Register.
DATACSN
I
Data Register Chip Select (For KSZ8862-32 Mode only)
This signal is used for central decoding architecture (mostly for embedded application).
When asserted, the device’s local decoding logic is ignored and the 32-bit access to QMU
Data Register is assumed.
INTRN
O
Interrupt
Synchronous Transfer Signals
VLBUSN
I
VLBUSN = 0, VLBus-like cycle.
VLBUSN = 1, burst cycle (both host/system and KSZ8862 can insert wait state)
CYCLEN
I
For VLBus-like access: used to sample SWR when asserted.
For burst access: used to connect to IOWC# bus signal to indicate burst write.
SWR
I
Write/Read
For VLBus-like access: used to indicate write (High) or read (Low) transfer.
For burst access: used to connect to IORC# bus signal to indicate burst read.
SRDYN
O
Synchronous Ready
For VLBus-like access: exactly the same signal definition of nSRDY in VLBus.
For burst access: insert wait state by the KSZ8862M whenever necessary during the Data
Register access.
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