参数资料
型号: PIC16LF72T-I/ML
厂商: Microchip Technology
文件页数: 78/136页
文件大小: 0K
描述: IC MCU FLASH 2KX14 LV AD 28-QFN
产品培训模块: Asynchronous Stimulus
标准包装: 1,600
系列: PIC® 16F
核心处理器: PIC
芯体尺寸: 8-位
速度: 20MHz
连通性: I²C,SPI
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 22
程序存储器容量: 3.5KB(2K x 14)
程序存储器类型: 闪存
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 2 V ~ 5.5 V
数据转换器: A/D 5x8b
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 28-VQFN 裸露焊盘
包装: 带卷 (TR)
PIC16F72
DS39597C-page 44
2007 Microchip Technology Inc.
REGISTER 9-1:
SSPSTAT: SYNCHRONOUS SERIAL PORT STATUS REGISTER (ADDRESS 94h)
R/W-0
R-0
SMP
CKE
D/A
PS
R/W
UA
BF
bit 7
bit 0
bit 7
SMP: SPI Data Input Sample Phase bits
SPI Master mode:
1
= Input data sampled at end of data output time
0
= Input data sampled at middle of data output time (Microwire)
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
I2C mode:
This bit must be maintained clear
bit 6
CKE: SPI Clock Edge Select bits (Figure 9-2, Figure 9-3, and Figure 9-4)
SPI mode, CKP = 0:
1
= Data transmitted on rising edge of SCK (Microwire alternate)
0
= Data transmitted on falling edge of SCK
SPI mode, CKP = 1:
1
= Data transmitted on falling edge of SCK (Microwire default)
0
= Data transmitted on rising edge of SCK
I2C mode:
This bit must be maintained clear
bit 5
D/A: Data/Address bit (I2C mode only)
1
= Indicates that the last byte received or transmitted was data
0
= Indicates that the last byte received or transmitted was address
bit 4
P: STOP bit (I2C mode only) – This bit is cleared when the SSP module is disabled, or when
the START bit is detected last. SSPEN is cleared.
1
= Indicates that a STOP bit has been detected last (this bit is ‘0’ on RESET)
0
= STOP bit was not detected last
bit 3
S: START bit (I2C mode only) – This bit is cleared when the SSP module is disabled, or when
the STOP bit is detected last. SSPEN is cleared.
1
= Indicates that a START bit has been detected last (this bit is ‘0’ on RESET)
0
= START bit was not detected last
bit 2
R/W: Read/Write Information bit (I2C mode only) – This bit holds the R/W bit information follow-
ing the last address match. This bit is only valid from the address match to the next START bit,
STOP bit, or ACK bit.
1
=Read
0
= Write
bit 1
UA: Update Address bit (10-bit I2C mode only)
1
= Indicates that the user needs to update the address in the SSPADD register
0
= Address does not need to be updated
bit 0
BF: Buffer Full Status bit
Receive (SPI and I2C modes):
1
= Receive complete, SSPBUF is full
0
= Receive not complete, SSPBUF is empty
Transmit (I2C mode only):
1
= Transmit in progress, SSPBUF is full
0
= Transmit complete, SSPBUF is empty
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
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