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参数资料
型号： PIC18LF2450T-I/SO
厂商： Microchip Technology
文件页数： 106/143页
文件大小： 0K
描述： IC PIC MCU FLASH 8KX16 28SOIC
标准包装： 1,600
系列： PIC® 18F
核心处理器： PIC
芯体尺寸： 8-位
速度： 48MHz
连通性： UART/USART，USB
外围设备： 欠压检测/复位，HLVD，POR，PWM，WDT
输入/输出数： 23
程序存储器容量： 16KB（8K x 16）
程序存储器类型： 闪存
RAM 容量： 768 x 8
电压 - 电源 (Vcc/Vdd)： 2 V ~ 5.5 V
数据转换器： A/D 10x10b
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 28-SOIC（0.295"，7.50mm 宽）
包装： 带卷 (TR)
PIC18F2450/4450
2006 Microchip Technology Inc.
Advance Information
DS39760A-page 63
TABLE 5-2:
REGISTER FILE SUMMARY (PIC18F2450/4450)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on page
TOSU
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000
49, 54
TOSH
Top-of-Stack High Byte (TOS<15:8>)
0000 0000
49, 54
TOSL
Top-of-Stack Low Byte (TOS<7:0>)
0000 0000
49, 54
STKPTR
STKFUL
STKUNF
—
SP4
SP3
SP2
SP1
SP0
00-0 0000
49, 55
PCLATU
—
Holding Register for PC<20:16>
---0 0000
49, 54
PCLATH
Holding Register for PC<15:8>
0000 0000
49, 54
PCL
PC Low Byte (PC<7:0>)
0000 0000
49, 54
TBLPTRU
—
—bit 21(1)
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
--00 0000
49, 76
TBLPTRH
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
0000 0000
49, 76
TBLPTRL
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
0000 0000
49, 76
TABLAT
Program Memory Table Latch
0000 0000
49, 76
PRODH
Product Register High Byte
xxxx xxxx
49, 83
PRODL
Product Register Low Byte
xxxx xxxx
49, 83
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
49, 87
INTCON2
RBPU
INTEDG0
INTEDG1
INTEDG2
—TMR0IP
—RBIP
1111 -1-1
49, 88
INTCON3
INT2IP
INT1IP
—
INT2IE
INT1IE
—INT2IF
INT1IF
11-0 0-00
49, 89
INDF0
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
N/A
49, 68
POSTINC0
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
N/A
49, 69
POSTDEC0
Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
N/A
49, 69
PREINC0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
N/A
49, 69
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
N/A
49, 69
FSR0H
—
Indirect Data Memory Address Pointer 0 High Byte
---- 0000
49, 68
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
xxxx xxxx
49, 68
WREG
Working Register
xxxx xxxx
49,
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
N/A
49, 68
POSTINC1
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
N/A
49, 69
POSTDEC1
Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
N/A
49, 69
PREINC1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
N/A
49, 69
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A
49, 69
FSR1H
—
Indirect Data Memory Address Pointer 1 High Byte
---- 0000
49, 68
FSR1L
Indirect Data Memory Address Pointer 1 Low Byte
xxxx xxxx
49, 68
BSR
—
Bank Select Register
---- 0000
49, 59
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
N/A
50, 68
POSTINC2
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
N/A
50, 69
POSTDEC2
Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
N/A
50, 69
PREINC2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
N/A
50, 69
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
N/A
50, 69
FSR2H
—
Indirect Data Memory Address Pointer 2 High Byte
---- 0000
50, 68
FSR2L
Indirect Data Memory Address Pointer 2 Low Byte
xxxx xxxx
50, 68
STATUS
—
—N
OV
Z
DC
C
---x xxxx
50, 66
TMR0H
Timer0 Register High Byte
0000 0000
50, 113
TMR0L
Timer0 Register Low Byte
xxxx xxxx
50, 113
T0CON
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
1111 1111
50, 111
Legend:
x
= unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note
1:
Bit 21 of the TBLPTRU allows access to the device Configuration bits.
2:
The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
3:
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
4:
RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
5:
RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’.
6:
RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
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