参数资料
型号: PIC18LF2450T-I/SO
厂商: Microchip Technology
文件页数: 86/143页
文件大小: 0K
描述: IC PIC MCU FLASH 8KX16 28SOIC
标准包装: 1,600
系列: PIC® 18F
核心处理器: PIC
芯体尺寸: 8-位
速度: 48MHz
连通性: UART/USART,USB
外围设备: 欠压检测/复位,HLVD,POR,PWM,WDT
输入/输出数: 23
程序存储器容量: 16KB(8K x 16)
程序存储器类型: 闪存
RAM 容量: 768 x 8
电压 - 电源 (Vcc/Vdd): 2 V ~ 5.5 V
数据转换器: A/D 10x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
包装: 带卷 (TR)
PIC18F2450/4450
2006 Microchip Technology Inc.
Advance Information
DS39760A-page 45
4.5
Device Reset Timers
PIC18F2450/4450 devices incorporate three separate
on-chip timers that help regulate the Power-on Reset
process. Their main function is to ensure that the
device clock is stable before code is executed. These
timers are:
Power-up Timer (PWRT)
Oscillator Start-up Timer (OST)
PLL Lock Time-out
4.5.1
POWER-UP TIMER (PWRT)
The Power-up Timer (PWRT) of the PIC18F2450/4450
devices is an 11-bit counter which uses the INTRC
source as the clock input. This yields an approximate
time interval of 2048 x 32
μs = 65.6 ms. While the
PWRT is counting, the device is held in Reset.
The power-up time delay depends on the INTRC clock
and will vary from chip to chip due to temperature and
process variation. See DC parameter 33 (Table 21-10)
for details.
The PWRT is enabled by clearing the PWRTEN
Configuration bit.
4.5.2
OSCILLATOR START-UP
TIMER (OST)
The Oscillator Start-up Timer (OST) provides a
1024 oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter 33, Table 21-10). This
ensures that the crystal oscillator or resonator has
started and stabilized.
The OST time-out is invoked only for XT, HS and
HSPLL modes and only on Power-on Reset or on exit
from most power-managed modes.
4.5.3
PLL LOCK TIME-OUT
With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly differ-
ent from other oscillator modes. A separate timer is
used to provide a fixed time-out that is sufficient for the
PLL to lock to the main oscillator frequency. This PLL
lock time-out (TPLL) is typically 2 ms and follows the
oscillator start-up time-out.
4.5.4
TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows:
1.
After the POR condition has cleared, PWRT
time-out is invoked (if enabled).
2.
Then, the OST is activated.
The total time-out will vary based on oscillator configu-
ration and the status of the PWRT. Figure 4-3,
depict time-out sequences on power-up, with the
Power-up Timer enabled and the device operating in
HS Oscillator mode. Figure 4-3 through Figure 4-6 also
apply to devices operating in XT mode. For devices in
RC mode and with the PWRT disabled, on the other
hand, there will be no time-out at all.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire.
Bringing MCLR high will begin execution immediately
(Figure 4-5). This is useful for testing purposes or to
synchronize more than one PIC18FXXXX device
operating in parallel.
TABLE 4-2:
TIME-OUT IN VARIOUS SITUATIONS
Oscillator
Configuration
Power-up(2) and Brown-out
Exit from
Power-Managed Mode
PWRTEN = 0
PWRTEN = 1
HS, XT
66 ms(1) + 1024 TOSC
1024 TOSC
HSPLL, XTPLL
66 ms(1) + 1024 TOSC + 2 ms(2)
1024 TOSC + 2 ms(2)
EC, ECIO
66 ms(1)
——
ECPLL, ECPIO
66 ms(1) + 2 ms(2)
2 ms(2)
INTIO, INTCKO
66 ms(1)
——
INTHS, INTXT
66 ms(1) + 1024 TOSC
1024 TOSC
Note 1:
66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2:
2 ms is the nominal time required for the PLL to lock.
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