SBSLITE Telecom Standard Product Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010883, Issue 2
241
Register 100H: Master Test
Bit
Type
Function
Default
Bit 15
Unused
X
Bit 14
Unused
X
Bit 13
Unused
X
Bit 12
Unused
X
Bit 11
Unused
X
Bit 10
Unused
X
Bit 9
Unused
X
Bit 8
Unused
X
Bit 7
Unused
X
Bit 6
R/W
Reserved
X
Bit 5
R/W
PMCATST
X
Bit 4
W
PMCTST
X
Bit 3
W
DBCTRL
0
Bit 2
R/W
IOTST
0
Bit 1
W
HIZDATA
0
Bit 0
R/W
HIZIO
0
This register is used to enable SBSLITE test features. All bits, except PMCTST and PMCATST
are reset to zero by a reset of the SBSLITE using either the RSTB input. PMCTST is reset when
CSB is logic one. PMCATST is reset when both CSB is high and RSTB is low. PMCTST and
PMCATST can also be reset by writing a logic zero to the corresponding register bit.
HIZIO, HIZDATA
The HIZIO and HIZDATA bits control the tri-state modes of the SBSLITE. While the HIZIO
bit is a logic one, all output pins of the SBSLITE except the data bus and output TDO are
held tri-state. The microprocessor interface is still active. While the HIZDATA bit is a logic
one, the data bus is also held in a high-impedance state which inhibits microprocessor read
cycles. The HIZDATA bit is overridden by the DBCTRL bit.
IOTST
The IOTST bit is used to allow normal microprocessor access to the test registers and control
the test mode in each TSB block in the SBSLITE for board level testing. When IOTST is a
logic one, all blocks are held in test mode and the microprocessor may write to a block’s test
mode 0 registers to manipulate the outputs of the block and consequently the device outputs.