SBSLITE Telecom Standard Product Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010883, Issue 2
30
Pin Name
Type
Pin
No.
Function
JTAG Interface (5 Signals)
TCK
Input
H13
Test Clock.
The JTAG test clock signal, TCK, provides timing for
test operations that are carried out using the IEEE P1149.1 test
access port.
TMS
Input
J11
Test Mode Select.
The JTAG test mode select signal, TMS,
controls the test operations that are carried out using the IEEE
P1149.1 test access port. TMS is sampled on the rising edge of
TCK. TMS has an integral pull-up resistor.
TDI
Input
J14
Test Data Input.
The JTAG test data input signal, TDI, carries test
data into the SBSLITE via the IEEE P1149.1 test access port. TDI
is sampled on the rising edge of TCK. TDI has an integral pull-up
resistor.
TDO
Tristate
H12
Test Data Output.
The JTAG test data output signal, TDO, carries
test data out of the SBSLITE via the IEEE P1149.1 test access
port. TDO is updated on the falling edge of TCK. TDO is a tri-state
output which is inactive except when scanning of data is in
progress.
TRSTB
Input
J12
Test Reset Bar.
The active low JTAG test reset signal, TRSTB,
provides an asynchronous SBSLITE test access port reset via the
IEEE P1149.1 test access port. TRSTB is a Schmitt triggered input
with an integral pull-up resistor.
Note that when TRSTB is not being used, it must be connected to
the RSTB input.
Analog Reference Resistors (2 Signals)
RES
Analog
Input
C2
Reference Resistor Connection (RES).
An off-chip 3.16k
±1%
resistor is connected between this positive resistor reference pin
and a Kelvin ground pin, RESK. An on-chip negative feedback path
will force the 0.8V VREF Voltage onto RES, therefore forcing
252uA of current to flow through the resistor.
RESK
Analog
Input
B2
Reference Resistor Connection (RESK).
An off-chip 3.16k
±1%
resistor is connected between the positive resistor reference pin,
RESK, and this Kelvin ground pin. An on-chip negative feedback
path will force the 0.8V VREF Voltage onto RESK, therefore forcing
252uA of current to flow through the resistor.
Analog Test Bus (2 Signals)
ATB0
Analog
F4
Analog test pin (ATB0).
This pin is used for PMC-Sierra validation
and testing. This pin must be grounded.
ATB1
Analog
F3
Analog test pin (ATB1).
This pin is used for PMC-Sierra validation
and testing. This pin must be grounded.
Analog High Voltage Power (5 Signals)
CSU_AVDH
Power
H1
CSU Analog Power (CSU_AVDH).
This pin should be connected
to a well-decoupled +3.3 V DC supply.