SBSLITE Telecom Standard Product Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010883, Issue 2
274
Figure 32 Incoming 77 MHz TelecomBus Functional Timing
SREFCLK
IDATA[7:0]
IPL
IC1FP(IC1J1V1)
ITPL
IV5
S4,3
A2
S1,1
J0
S2,1
Z0
S3,1
Z0
S4,1
Z0
S1,2
Z0
S2,2
Z0
S3,2
Z0
S4,2
Z0
S1,3
Z0
S2,3
Z0
S3,3
Z0
S4,3
Z0
S1,1
B522
S2,1
B522
S3,1
B522
S4,1
B522
S1,1
H3
S2,1
H3
S3,1
H3
S4,1
H3
S1,2
H3
S2,2
H3
S3,2
H3
S4,2
H3
S1,3
H3
S2,3
H3
S3,3
H3
S4,3
H3
S4,3
H2
S1,1
B0
S2,1
B0
S3,1
B0
S4,1
B0
S1,2
B0
S2,2
B0
S3,2
B0
ITAIS
.
.
.
IDP
ICMP
.
.
.
.
.
.
Vaild
X
X
X
X
X
X
X
14.3
Transmit Serial LVDS Functional Timing
The delay through the SBSLITE is dependent on the operating mode. The timing from the
Incoming telecom or SBI bus to the LVDS link differs between TelecomBus mode and SBI mode.
The timing when in SBI mode is also dependent on whether the SBSLITE is switching at the DS0
level and above or is switching only at the tributary level. When switching only tributaries in SBI
mode we have the same delay through the SBSLITE as when switching tributaries in TelecomBus
mode.
When switching tributaries in SBI mode or when in TelecomBus mode, the SBSLITE is acting as
a column switch and introduces a minimum delay equivalent to one row in a 77.76 MHz
TelecomBus structure or SBI336 bus structure. This minimum delay equates to 1080 SYSCLK
cycles. The actual delay will be slightly longer by no more than 31 SYSCLK cycles to allow for
other data path delays within the SBSLITE.
Figure 33 Incoming TelecomBus to LVDS Functional Timing
S4,3 / A2
TNWRK/
TPWRK
S1,1 / J0
S2,1 / Z0
TNPROT/
TPPROT
...
Minimum Delay, 1080 + 23 cycles
...
SYSCLK
IPL
Maximum Delay, 1080 + 31 cycles
IC1FP (IJ0J1V1)
S1,1 / J0
...
...
TC1FP
Delay J0 on IJ0J1V1 to TC1FP, 1080 + 32 cycles