SBSLITE Telecom Standard Product Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010883, Issue 2
58
Code Group
Name
Curr. RD-
abcdei fghj
Curr. RD+
abcdei fghj
Encoded Signals
Description
and REI are encoded in the V5 byte.
K29.7-
101110 1000
-
IV5=’b1,
IDATA[0,4] = ERDI[1:0] = ‘b10, IDATA[5] =
REI = ‘b0
Low order path frame alignment. ERDI
and REI are encoded in the V5 byte.
K29.7+
-
010001 0111
IV5=’b1,
IDATA[0,4] = ERDI[1:0] = ‘b10, IDATA[5] =
REI = ‘b1
Low order path frame alignment. ERDI
and REI are encoded in the V5 byte.
K30.7-
011110 1000
-
IV5=’b1,
IDATA[0,4] = ERDI[1:0] = ‘b11, IDATA[5] =
REI = ‘b0
Low order path frame alignment. ERDI
and REI are encoded in the V5 byte.
K30.7+
-
100001 0111
IV5=’b1,
IDATA[0,4] = ERDI[1:0] = ‘b11, IDATA[5] =
REI = ‘b1
Low order path frame alignment. ERDI
and REI are encoded in the V5 byte.
K23.7-
111010 1000
000101 0111
ITPL=’b0
Non low-order path payload bytes.
10.9
Transmit Serializer
The Transmit Serializer blocks, TWPS and TPPS, convert 8B/10B characters to bit-serial format.
The Transmit Working Serializer, TWPS, generates a serial stream for the working transmit
LVDS link, TPWRK/TNWRK. The Transmit Protect Serializer, TPPS, generates a serial stream
for the protect transmit LVDS link, TPPROT/TNPROT.
10.10 LVDS Transmitters
The LVDS Transmitters, TWLV and TPLV, convert 8B/10B encoded digital bit-serial streams to
LVDS signaling levels. The Transmit Working LVDS Interface, TWLV, drives the working
transmit LVDS links, TPWRK/TNWRK. The Transmit Protect LVDS Interface block, TPLV,
drives the protect transmit LVDS link, TPPROT/TNPROT.
10.11 Clock Synthesis Unit
The Clock Synthesis Unit (CSU) block generates the 777.6 MHz clock for the transmit and
receive LVDS links.
10.12 Transmit Reference Generator
The Transmit Voltage Reference Generator block generates bias voltages and currents for the
LVDS Transmitters.