SBSLITE Telecom Standard Product Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010883, Issue 2
98
Register 020H: ISTA Incoming Parity Configuration
Bit
Type
Function
Default
Bit 15
R/W
Reserved
0
Bit 14
R/W
Reserved
0
Bit 13
R/W
Reserved
0
Bit 12
R/W
IPE
0
Bit 11
R/W
Reserved
0
Bit 10
R/W
Reserved
0
Bit 9
R/W
Reserved
0
Bit 8
R/W
INCLIC1
0
Bit 7
R/W
Reserved
0
Bit 6
R/W
Reserved
0
Bit 5
R/W
Reserved
0
Bit 4
R/W
INCLIPL
0
Bit 3
R/W
Reserved
0
Bit 2
R/W
Reserved
0
Bit 1
R/W
Reserved
0
Bit 0
R/W
IOP
0
Reserved
The Reserved bits must be set to a logic zero.
IPE
The incoming parity interrupt enable bit (IPE) is an active high interrupt enable. When IPE is
set to a logic one, the occurrence of a parity error on the incoming bus will cause an interrupt
to be asserted on the INTB output. When IPE is set to a logic zero, incoming parity errors
will not cause and interrupt.
INCLIPL
The INCLIPL bit controls whether the IPL input signal participates in the incoming parity
calculations. When INCLIPL is set to a logic one, the parity signal includes the IPL input.
When INCLIPL is set to a logic zero, parity is calculated without regard to the state of IPL.
These bits only take effect when in TelecomBus mode.
INCLIC1
The INCLIC1 bit controls whether the IC1FP input signal participates in the incoming parity
calculations. When INCLIC1 is set to a logic one, the parity signal includes the IC1FP input.
When INCLIC1 is set to a logic zero, parity is calculated without regard to the state of IC1FP.
These bits only take effect when in TelecomBus mode.