参数资料
型号: PSD835G2V-C-12M
厂商: 意法半导体
英文描述: Configurable Memory System on a Chip for 8-Bit Microcontrollers
中文描述: 在8片位微控制器可配置存储系统
文件页数: 24/110页
文件大小: 570K
代理商: PSD835G2V-C-12M
PSD835G2
PSD8XX Family
19
The
PSD835G2
Functional
Blocks
(cont.)
FS0-7
or
Instruction
CSBOOT0-3 Cycle 1 Cycle 2 Cycle 3
Cycle 4
Cycle5
Cycle 6
Cycle 7
Read (Note 5)
1
“Read”
RA RD
Read Main Flash ID
1
AAh
55h
90h
“Read”
(Notes 6,13)
@555h
@AAAh
@555h
ID
@x01h
Read Sector Protection
1
AAh
55h
90h
“Read”
(Notes 6,8,13)
@555h
@AAAh
@555h
00h or 01h
@x02h
Program a Flash Byte
1
AAh
55h
A0h
PD@PA
@555h
@AAAh
@555h
Erase One Flash Sector
1
AAh
55h
80h
AAh
55h
30h
@555h
@AAAh
@555h
@AAAh
@SA
@next SA
(Note 7)
Erase Flash Block
1
AAh
55h
80h
AAh
55h
10h
(Bulk Erase)
@555h
@AAAh
@555h
@AAAh
@555h
Suspend Sector Erase
1
B0h
(Note 11)
@xxxh
Resume Sector Erase
1
30h
(Note 12)
@xxxh
Reset (Note 6)
1
F0 @ any
address
Unlock Bypass
1
AAh
55h
20h
@555h
@AAAh
@555h
Unlock Bypass Program
1
A0h
PD@PA
(Note 9)
@xxxh
Unlock Bypass Reset
1
90h
00h
(Note 10)
@xxxh
Table 8. Instructions
X
= Don’t Care.
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WR#
(CNTL0) pulse.
PD = Data to be programmed at location PA. Data is latched o the rising edge of WR# (CNTL0) pulse.
SA = Address of the sector to be erased or verified. The chip select (FS0-7 or CSBOOT0-3) of the sector to be
erased must be active (high).
NOTES:
1.
All bus cycles are write bus cycle except the ones with the “read” label.
2.
All values are in hexadecimal.
3.
FS0-7 and CSBOOT0-3 are active high and are defined in PSDsoft.
4.
Only Address bits A11-A0 are used in Instruction decoding. A15-12 (or A16-A12) are don’t care.
5.
No unlock or command cycles required when device is in read mode.
6.
The Reset command is required to return to the read mode after reading the Flash ID, Sector Protect status
or if DQ5 (error flag) goes high.
7.
Additional sectors to be erased must be entered within 80s.
8.
The data is 00h for an unprotected sector and 01h for a protected sector. In the fourth cycle, the sector chip
select is active and (A1 = 1, A0 = 0).
9.
The Unlock Bypass command is required prior to the Unlock Bypass Program command.
10. The Unlock Bypass Reset command is required to return to reading array data when the device is in the
Unlock Bypass mode.
11. The system may read and program functions in non-erasing sectors, read the Flash ID or read the Sector
Protect status, when in the Erase Suspend mode. The erase Suspend command is valid only during a sector
erase operation.
12. The Erase Resume command is valid only during the Erase Suspend mode.
13. The MCU cannot invoke these instructions while executing code from the same Flash memory for which the
instruction is intended. The MCU must fetch, for example, codes from the secondary block when reading the
Sector Protection Status of the main Flash.
相关PDF资料
PDF描述
PSD835G2V-C-12JI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G2V-C-12J Configurable Memory System on a Chip for 8-Bit Microcontrollers
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