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参数资料
型号： PSD835G2V-C-12M
厂商： 意法半导体
英文描述： Configurable Memory System on a Chip for 8-Bit Microcontrollers
中文描述： 在8片位微控制器可配置存储系统
文件页数： 44/110页
文件大小： 570K
代理商： PSD835G2V-C-12M
PSD8XX Family
PSD835G2
38
The
PSD835G2
Functional
Blocks
(cont.)
9.2.2.1 Output Micro
Cell
Eight of the Output Micro
Cells are connected to Port A pins are named as McellA0-7.
The other eight Micro
Cells are connected to Port B pins are named as McellB0-7.
Maximum
Native
Borrowed
Data Bit for
Output
Port
Product
Loading or
Micro
Cell
Assignment
Terms
Reading
McellA0
Port A0
3
6
D0
McellA1
Port A1
3
6
D1
McellA2
Port A2
3
6
D2
McellA3
Port A3
3
6
D3
McellA4
Port A4
3
6
D4
McellA5
Port A5
3
6
D5
McellA6
Port A6
3
6
D6
McellA7
Port A7
3
6
D7
McellB0
Port B0
4
5
D0
McellB1
Port B1
4
5
D1
McellB2
Port B2
4
5
D2
McellB3
Port B3
4
5
D3
McellB4
Port B4
4
6
D4
McellB5
Port B5
4
6
D5
McellB6
Port B6
4
6
D6
McellB7
Port B7
4
6
D7
Table 13. Output Micro
Cell Port and Data Bit Assignments
The Output Micro
Cell (OMC) architecture is shown in Figure 13. As shown in the figure,
there are native product terms available from the AND array, and borrowed product terms
available (if unused) from other OMCs. The polarity of the product term is controlled by the
XOR gate. The OMC can implement either sequential logic, using the flip-flop element, or
combinatorial logic. The multiplexer selects between the sequential or combinatorial logic
outputs. The multiplexer output can drive a Port pin and has a feedback path to the AND
array inputs.
The flip-flop in the OMC can be configured as a D, T, JK, or SR type in the PSDsoft
program. The flip-flop’s clock, preset, and clear inputs may be driven from a product term
of the AND array. Alternatively, the external CLKIN signal can be used for the clock input
to the flip-flop. The flip-flop is clocked on the rising edge of the clock input. The preset and
clear are active-high inputs. Each clear input can use up to two product terms.
相关PDF资料
PDF描述
PSD835G2V-C-12JI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G2V-C-12J Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G2V-C-70B81I Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G2V-C-70J Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G2V-C-70JI Configurable Memory System on a Chip for 8-Bit Microcontrollers
相关代理商/技术参数
参数描述
PSD853F2-70J 功能描述:SPLD - 简单可编程逻辑器件 5.0V 1M 70ns RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24
PSD853F2-70M 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 1M 70ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
PSD853F2-90J 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
PSD853F2-90JI 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
PSD853F2-90M 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
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