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| 型号： | PSD835G2V-C-12M |
| 厂商： | 意法半导体 |
| 英文描述： | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| 中文描述： | 在8片位微控制器可配置存储系统 |
| 文件页数： | 63/110页 |
| 文件大小： | 570K |
| 代理商： | PSD835G2V-C-12M |
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PSD835G2
PSD8XX Family
55
The
PSD835G2
Functional
Blocks
(cont.)
Control
Direction
VM
Defined In
Register
JTAG
Mode
PSDsoft
Setting
Enable
Declare
0
1 = output,
MCU I/O
pins only
(Note 3)
0 = input
NA
(Note 1)
Declare pins
PLD I/O
and logic
NA
(Note 1)
NA
equations
Data Port
Selected for
(Port F)
MCU with
NA
non-mux bus
Address Out
Declare
1
1 (Note 1)
NA
(Port E, F, G)
pins only
Declare pins or
Address In
logic equation
NA
(Port A,B,C,D,F) for input
Micro
Cells
Peripheral I/O
Logic equations
NA
PIO bit = 1
NA
(Port F)
(PSEL0 & 1)
JTAG ISP
Declare pins
NA
JTAG_Enable
(Note 2)
only
Table 17. Port Operating Mode Settings
*NA = Not Applicable
NOTE: 1. The direction of the Port A,B,C, and F pins are controlled by the Direction Register ORed with the
individual output enable product term (.oe) from the CPLD AND array.
2. Any of these three methods will enable JTAG pins on Port E.
3. Control Register setting is not applicable to Ports A, B and C.
9.4.2.1 MCU I/O Mode
In the MCU I/O Mode, the microcontroller uses the PSD835G2 ports to expand its own
I/O ports. By setting up the CSIOP space, the ports on the PSD4000 are mapped into the
microcontroller address space. The addresses of the ports are listed in Table 6.
A port pin can be put into MCU I/O mode by writing a ‘0’ to the corresponding bit in the
Control Register (Port E, F and G). The MCU I/O direction may be changed by writing to
the corresponding bit in the Direction Register, or by the output enable product term. See
the subsection on the Direction Register in the “Port Registers” section. When the pin is
configured as an output, the content of the Data Out Register drives the pin. When config-
ured as an input, the microcontroller can read the port input through the Data In buffer.
See Figure 22.
Ports A, B and C do not have Control Registers, and are in MCU I/O mode by default.
They can be used for PLD I/O if they are specified in PSDsoft.
9.4.2.2 PLD I/O Mode
The PLD I/O Mode uses a port as an input to the CPLD’s Input Micro
Cells, and/or as an
output from the CPLD’s Output Micro
Cells. The output can be tri-stated with a control
signal. This output enable control signal can be defined by a product term from the PLD, or
by setting the corresponding bit in the Direction Register to ‘0’. The corresponding bit in the
Direction Register must not be set to ‘1’ if the pin is defined as a PLD input pin in PSDsoft.
The PLD I/O Mode is specified in PSDsoft by declaring the port pins, and then specifying
an equation in PSDsoft.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PSD853F2-70J | 功能描述:SPLD - 简单可编程逻辑器件 5.0V 1M 70ns RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24 |
| PSD853F2-70M | 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 1M 70ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| PSD853F2-90J | 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| PSD853F2-90JI | 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| PSD853F2-90M | 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
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