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参数资料
| 型号： | QL5810-66CPTN196I |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA196 |
| 封装： | 12 X 12 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, PLASTIC, MO-216C, TFBGA-196 |
| 文件页数： | 42/80页 |
| 文件大小： | 1125K |
| 代理商： | QL5810-66CPTN196I |
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2006 QuickLogic Corporation
QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. L
47
Pin Descriptions
Table 31: Pin Descriptions
Pin
Direction
Function
Description
JTAG Pin Descriptions
TDI/RSI
I
Test Data In for JTAG/RAM init.
Serial Data In
Hold HIGH during normal operation. Connects to serial
PROM data in for RAM initialization. Connect to
VDED2 if unused
TRSTB/RRO
I/0
Active low Reset for JTAG/RAM
init. reset out
Hold LOW during normal operation. Connects to serial
PROM reset for RAM initialization. Connect to GND if
unused
TMS
I
Test Mode Select for JTAG
Hold HIGH during normal operation. Connect to
VDED2 if not used for JTAG
TCK
I
Test Clock for JTAG
Hold HIGH or LOW during normal operation. Connect
to VDED2 or GND if not used for JTAG
TDO/RCO
O
Test data out for JTAG/RAM init.
clock out
Connect to serial PROM clock for RAM initialization.
Must be left unconnected if not used for JTAG or RAM
initialization. The output voltage drive is specified by
VDED.
Dedicated Pin Descriptions
CLK
I
Global clock network pin
Low skew global clock. This pin provides access to a
dedicated, distributed network capable of driving the
CLOCK, SET, RESET, F1, and A2 inputs to the Logic
Cell, READ, and WRITE CLOCKS, Read and Write
Enables of the Embedded RAM Blocks, CLOCK of the
ECUs, and Output Enables of the I/Os. The voltage
tolerance of this pin is specified by VDED.
I/O(A)
I/O
Input/Output pin
The I/O pin is a bi-directional pin, configurable to either
an input-only, output-only, or bi-directional pin. The A
inside the parenthesis means that the I/O is located in
Bank A. If an I/O is not used, SpDE (QuickWorks Tool)
provides the option of tying that pin to GND, VCC, or
TriState.
VCC
I
Power supply pin
Connect to 1.8 V supply.
VCCIO(A)
I
Input voltage tolerance pin
This pin provides the flexibility to interface the device
with either a 3.3 V, 2.5 V, or 1.8 V device. The A inside
the parenthesis means that VCCIO is located in BANK
A. Every I/O pin in Bank A will be tolerant of VCCIO
input signals and will drive VCCIO level output signals.
This pin must be connected to either 3.3 V, 2.5 V, or 1.8
V. VCCIO powers the the PLLOUT pins.
GND
I
Ground pin
Connect to ground.
PLLIN
I
PLL clock input
Clock input for PLL. The voltage tolerance of this pin is
specified by VDED.
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