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参数资料
| 型号： | QL5810-66CPTN196I |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA196 |
| 封装： | 12 X 12 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, PLASTIC, MO-216C, TFBGA-196 |
| 文件页数： | 78/80页 |
| 文件大小： | 1125K |
| 代理商： | QL5810-66CPTN196I |
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2006 QuickLogic Corporation
QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. L
8
QuickWorks Design Software
The QuickWorks package provides the most complete ESP and FPGA software solution from design entry to
logic synthesis, to place and route, to power calculation, and simulation. The package provides a solution for
designers who use third-party tools from Cadence, Mentor, OrCAD, Synopsys, Viewlogic, and other third-
party tools for design entry, synthesis, or simulation.
Process Data
The QL58x0 device family is fabricated on a 0.18
μ, six layer metal CMOS process. The core voltage is 1.8 V
and the I/Os are up to 3.3 V drive/tolerant. The QL58x0 device family product line is available in commercial,
industrial, and military temperature grades.
Programmable Logic Architectural Overview
The QL58x0 device family logic cell structure is presented in Figure 3. This architectural feature addresses
today's register-intensive designs.
Table 6: Device Speed Grade and Operating Rangea Package Availability
a. C = Commercial
I
= Industrial
M = Military
Device
144 TQFP
196 TFBGA
208 PQFP
280 LFBGA
484 PBGA
QL5810
33A (C, I, & M)
33B (C, I, & M)
66C (C & I)
33A (C, I, & M)
33B (C, I, & M)
66C (C & I)
--
-
QL5820
33A (C, I, & M)
33B (C, I, & M)
66C (C & I)
33A (C, I, & M)
33B (C, I, & M)
66C (C, I, & M)
33A (C, I, & M)
33B (C, I, & M)
66C (C, I, & M)
33A (C, I, & M)
33B (C, I, & M)
-
QL5840
-
33A (C, I, & M)
33B (C, I, & M)
33A (C, I, & M)
33B (C, I, & M)
66C (C & I)
33A (C, I, & M)
33B (C, I, & M)
66C (C, I, & M)
Table 7: Performance Standardsa
a. Performance standards for worst-case commercial conditions.
Function
Description
Slowest Speed Grade
Fastest Speed Grade
Multiplexer
16:1
2.8 ns
2.4 ns
Parity Tree
24
3.4 ns
2.9 ns
36
4.6 ns
3.9 ns
Counter
16 bit
275 MHz
328 MHz
32 bit
250 MHz
300 MHz
Synchronous
FIFO
128 x 32
197 MHz
235 MHz
128 x 64
188 MHz
266 MHz
256 x 16
208 MHz
248 MHz
Clock-to-Out
6.5 ns
6 ns
System Clock
200 MHz
300 MHz
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