Datasheet
53
Signal Definitions
STPCLK#
I
STPCLK# (Stop Clock), when asserted, causes processors to enter a low
power Stop-Grant state. The processor issues a Stop-Grant Acknowledge
transaction, and stops providing internal clock signals to all processor core
units except the front side bus and APIC units. The processor continues to
snoop bus transactions and service interrupts while in Stop-Grant state.
When STPCLK# is deasserted, the processor restarts its internal clock to
all units and resumes execution. The assertion of STPCLK# has no effect
on the bus clock; STPCLK# is an asynchronous input.
3
TCK
I
TCK (Test Clock) provides the clock input for the processor Test Bus (also
known as the Test Access Port).
TDI
I
TDI (Test Data In) transfers serial test data into the processor. TDI provides
the serial input needed for JTAG specification support.
TDO
O
TDO (Test Data Out) transfers serial test data out of the processor. TDO
provides the serial output needed for JTAG specification support.
TEST_BUS
I
Must be connected to all other processor TEST_BUS signals in the
system.
TESTHI[6:0]
I
All TESTHI inputs should be individually connected to VTT via a pull-up
resistor which matches the trace impedance. TESTHI[3:0] and
TESTHI[6:5] may all be tied together and pulled up to VTT with a single
resistor if desired. However, utilization of boundary scan test will not be
functional if these pins are connected together. TESTHI4 must always be
pulled up independently from the other TESTHI pins. For optimum noise
margin, all pull-up resistor values used for TESTHI[6:0] should have a
resistance value within
± 20% of the impedance of the baseboard
transmission line traces. For example, if the trace impedance is 50
, than
a value between 40
and 60 should be used.
THERMDA
Other
THERMDC
Other
THERMTRIP#
O
Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction
temperature has reached a temperature beyond which permanent silicon
damage may occur. Measurement of the temperature is accomplished
through an internal thermal sensor. Upon assertion of THERMTRIP#, the
processor will shut off its internal clocks (thus halting program execution) in
an attempt to reduce the processor junction temperature. To protect the
processor its core voltage (VCC) must be removed following the assertion
of THERMTRIP#.
Driving of the THERMTRIP# signals is enabled within 10 ms of the
assertion of PWRGOOD and is disabled on de-assertion of PWRGOOD.
Once activated, THERMTRIP# remains latched until PWRGOOD is de-
asserted. While the de-assertion of the PWRGOOD signal will de-assert
THERMTRIP#, if the processor’s junction temperature remains at or above
the trip level, THERMTRIP# will again be asserted within 10 ms of the
assertion of PWRGOOD.
2
TMS
I
TMS (Test Mode Select) is a JTAG specification support signal used by
debug tools.
This signal does not have on-die termination and must be terminated
at the end agent.
TRDY#
I
TRDY# (Target Ready) is asserted by the target to indicate that it is ready
to receive a write or implicit writeback data transfer. TRDY# must connect
the appropriate pins of all front side bus agents.
TRST#
I
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must
be driven low during power on Reset.
VCCA
I
VCCA provides isolated power for the analog portion of the internal
processor core PLL’s. Refer to the appropriate platform design guidelines
for complete implementation details.
Table 4-1. Signal Definitions (Sheet 9 of 10)
Name
Type
Description
Notes