Datasheet
87
Features
7.2.3
Stop Grant State
When the STPCLK# pin is asserted, the Stop Grant state of the processor is entered 20 bus clocks
after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. Once
the STPCLK# pin has been asserted, it may only be deasserted once the processor is in the Stop
Grant state. For the 64-bit Intel Xeon processor with 2 MB L2 cache, both logical processors must
be in the Stop Grant state before the deassertion of STPCLK#.
Since the AGTL+ signal pins receive power from the front side bus, these pins should not be driven
(allowing the level to return to VTT) for minimum power drawn by the termination resistors in this
state. In addition, all other input pins on the front side bus should be driven to the inactive state.
BINIT# will not be serviced while the processor is in Stop Grant state. The event will be latched
and can be serviced by software upon exit from the Stop Grant state.
RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop
Grant state. A transition back to the Normal state will occur with the de-assertion of the STPCLK#
signal. When re-entering the Stop Grant state from the Sleep state, STPCLK# should only be
deasserted one or more bus clocks after the deassertion of SLP#.
Figure 7-1. Stop Clock State Machine
Enhanced HALT or HALT State
BCLK running
Snoops and interrupts allowed
Normal State
Normal execution
Enhanced HALT Snoop or HALT
Snoop State
BCLK running
Service snoops to caches
Stop Grant State
BCLK running
Snoops and interrupts allowed
Sleep State
BCLK running
No snoops or interrupts
allowed
Snoop
Event
Occurs
Snoop
Event
Serviced
INIT#, BINIT#, INTR, NMI, SMI#,
RESET#, FSB interrupts
STPCLK#
Asserted
STPCLK#
De-asserted
S
TP
C
LK
#
A
ss
er
te
d
S
TP
C
LK
#
D
e-
as
se
rte
d
SLP#
Asserted
SLP#
De-asserted
Snoop Event Occurs
Snoop Event Serviced
HALT or MWAIT Instruction and
HALT Bus Cycle Generated
Stop Grant Snoop State
BCLK running
Service snoops to caches