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参数资料
| 型号： | RK80546KG1042MM |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 3600 MHz, MICROPROCESSOR, CPGA604 |
| 封装： | FLIP CHIP, MICRO PGA-604 |
| 文件页数： | 50/106页 |
| 文件大小： | 4724K |
| 代理商： | RK80546KG1042MM |
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48
Datasheet
Signal Definitions
D[63:0]#
I/O
D[63:0]# (Data) are the data signals. These signals provide a 64-bit data
path between the processor front side bus agents, and must connect the
appropriate pins on all such agents. The data driver asserts DRDY# to
indicate a valid data transfer.
D[63:0]# are quad-pumped signals, and will thus be driven four times in a
common clock period. D[63:0]# are latched off the falling edge of both
DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond
to a pair of one DSTBP# and one DSTBN#. The following table shows the
grouping of data signals to strobes and DBI#.
Furthermore, the DBI# pins determine the polarity of the data signals. Each
group of 16 data signals corresponds to one DBI# signal. When the DBI#
signal is active, the corresponding data group is inverted and therefore
sampled active high.
4
DBI[3:0]#
I/O
DBI[3:0]# are source synchronous and indicate the polarity of the D[63:0]#
signals. The DBI[3:0]# signals are activated when the data on the data bus
is inverted. If more than half the data bits, within a 16-bit group, would have
been asserted electronically low, the bus agent may invert the data bus
signals for that particular sub-phase for that 16-bit group.
4
DBSY#
I/O
DBSY# (Data Bus Busy) is asserted by the agent responsible for driving
data on the processor front side bus to indicate that the data bus is in use.
The data bus is released after DBSY# is deasserted. This signal must
connect the appropriate pins on all processor front side bus agents.
4
DEFER#
I
DEFER# is asserted by an agent to indicate that a transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the
responsibility of the addressed memory or I/O agent. This signal must
connect the appropriate pins of all processor front side bus agents.
4
DP[3:0]#
I/O
DP[3:0]# (Data Parity) provide parity protection for the D[63:0]# signals.
They are driven by the agent responsible for driving D[63:0]#, and must
connect the appropriate pins of all processor front side bus agents.
4
DRDY#
I/O
DRDY# (Data Ready) is asserted by the data driver on each data transfer,
indicating valid data on the data bus. In a multi-common clock data
transfer, DRDY# may be deasserted to insert idle clocks. This signal must
connect the appropriate pins of all processor front side bus agents.
4
Table 4-1. Signal Definitions (Sheet 4 of 10)
Name
Type
Description
Notes
Data Group
DSTBN#/
DSTBP#
DBI#
D[15:0]#
0
D[31:16]#
1
D[47:32]#
2
D[63:48]#
3
DBI[3:0] Assignment To Data Bus
Bus Signal
Data Bus Signals
DBI0#
D[15:0]#
DBI1#
D[31:16]#
DBI2#
D[47:32]#
DBI3#
D[63:48]#
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