86
Datasheet
Features
asserting the Stop Grant SBC on the bus before allowing the processor to be transitioned into one
of the lower processor power states. Refer to the applicable chipset specification for more
information.
Due to the inability of processors to recognize bus transactions during the Sleep state,
multiprocessor systems are not allowed to simultaneously have one processor in Sleep state and the
other processors in Normal or Stop Grant state.
7.2.1
Normal State
This is the normal operating state for the processor.
7.2.2
HALT or Enhanced HALT Power Down States
The Enhanced HALT Power Down state is configured and enabled via the BIOS. If the Enhanced
HALT state is not enabled, the default Power Down state entered will be HALT. Refer to the
sections below for details on HALT and Enhanced HALT states.
7.2.2.1
HALT Power Down State
HALT is a low power state entered when the processor executes the HALT or MWAIT instruction.
When one of the logical processors executes the HALT or MWAIT instruction, that logical
processor is halted; however, the other processor continues normal operation. The processor will
transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, LINT[1:0] (NMI,
INTR), or an interrupt delivered over the front side bus. RESET# will cause the processor to
immediately initialize itself.
The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or
the HALT Power Down state. See the IA-32 Intel Architecture Software Developer's Manual,
Volume 3: System Programmer's Guide for more information.
The system can generate a STPCLK# while the processor is in the HALT Power Down state. When
the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state.
While in HALT Power Down state, the processor will process front side bus snoops and interrupts.
7.2.2.2
Enhanced HALT Power Down State
Enhanced HALT state is a low power state entered when all logical processors have executed the
HALT or MWAIT instructions and Enhanced HALT state has been enabled via the BIOS. When
one of the logical processors executes the HALT instruction, that logical processor is halted;
however, the other processor continues normal operation. The Enhanced HALT state is generally a
lower power state than the Stop Grant state.
The processor will automatically transition to a lower core frequency and voltage operating point
before entering the Enhanced HALT state. Note that the processor FSB frequency is not altered;
only the internal core frequency is changed. When entering the low power state, the processor will
first switch to the lower bus ratio and then transition to the lower VID.
While in the Enhanced HALT state, the processor will process bus snoops.
The processor exits the Enhanced HALT state when a break event occurs. When the processor
exists the Enhanced HALT state, it will first transition the VID to the original value and then
change the bus ratio back to the original value.