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参数资料
| 型号： | RK80546KG1042MM |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 3600 MHz, MICROPROCESSOR, CPGA604 |
| 封装： | FLIP CHIP, MICRO PGA-604 |
| 文件页数： | 51/106页 |
| 文件大小： | 4724K |
| 代理商： | RK80546KG1042MM |
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Datasheet
49
Signal Definitions
DSTBN[3:0]#
I/O
Data strobe used to latch in D[63:0]#.
4
DSTBP[3:0]#
I/O
Data strobe used to latch in D[63:0]#.
4
FERR#/PBE#
O
FERR#/PBE# (floating-point error/pending break event) is a multiplexed
signal and its meaning is qualified by STPCLK#. When STPCLK# is not
asserted, FERR#/PBE# indicates a floating-point error and will be asserted
when the processor detects an unmasked floating-point error. When
STPCLK# is not asserted, FERR#/PBE# is similar to the ERROR# signal
on the Intel 387 coprocessor, and is included for compatibility with systems
using MS-DOS*-type floating-point error reporting. When STPCLK# is
asserted, an assertion of FERR#/PBE# indicates that the processor has a
pending break event waiting for service. The assertion of FERR#/PBE#
indicates that the processor should be returned to the Normal state. For
additional information on the pending break event functionality, including
the identification of support of the feature and enable/disable information,
refer to Vol. 3 of the IA-32 Intel Architecture Software Developer’s Manual
and the Intel Processor Identification and the CPUID Instruction application
note.
This signal does not have on-die termination and must be terminated
at the end agent.
3
FORCEPR#
I
The FORCEPR# input can be used by the platform to force the processor
to activate the Thermal Control Circuit (TCC). The TCC will remain active
until the system deasserts FORCEPR#.
GTLREF
I
GTLREF determines the signal reference level for GTL+ input pins.
GTLREF is used by the GTL+ receivers to determine if a signal is a logical
0 or a logical 1.
HIT#
HITM#
I/O
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop
operation results. Any front side bus agent may assert both HIT# and
HITM# together to indicate that it requires a snoop stall, which can be
continued by reasserting HIT# and HITM# together.
Since multiple agents may deliver snoop results at the same time, HIT#
and HITM# are wired-OR signals which must connect the appropriate pins
of all processor front side bus agents. In order to avoid wired-OR glitches
associated with simultaneous edge transitions driven by multiple drivers,
HIT# and HITM# are activated on specific clock edges and sampled on
specific clock edges.
4
Table 4-1. Signal Definitions (Sheet 5 of 10)
Name
Type
Description
Notes
Signals
Associated Strobes
D[15:0]#, DBI0#
DSTBN0#
D[31:16]#, DBI1#
DSTBN1#
D[47:32]#, DBI2#
DSTBN2#
D[63:48]#, DBI3#
DSTBN3#
Signals
Associated Strobes
D[15:0]#, DBI0#
DSTBP0#
D[31:16]#, DBI1#
DSTBP1#
D[47:32]#, DBI2#
DSTBP2#
D[63:48]#, DBI3#
DSTBP3#
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相关代理商/技术参数 |
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| RK80546KG1122MM | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Intel 功能描述: |
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