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| 型号： | S1R72105F00A000 |
| 元件分类： | 总线控制器 |
| 英文描述： | SCSI BUS CONTROLLER, PQFP100 |
| 封装： | 0.50 MM PITCH, PLASTIC, QFP15-100 |
| 文件页数： | 16/99页 |
| 文件大小： | 666K |
| 代理商： | S1R72105F00A000 |
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S1R72105 Technical Manual
Rev.1.0
EPSON
17
7.3
Detailed Description of Each Register
7.3.1
Main Interrupt Status (MainIntStat)
R/W
When the IC interrupts the CPU, the CPU identifies the interrupt status register responsible for interruption by
reading this register first.
Following the reading of this register, the CPU identifies the bit as a source of interruption and clears it by
writing the value read after appropriate interrupt processing.
When the EPrIntStat is a source of interruption, the bit should be cleared by writing the value read to the
interrupt status register corresponding to each bit of the interrupt status register.
Address
Register Name
Bit Symbol
Description
00h
MainIntStat
7: USBresume
USB Resume
6: USBreset
USB Reset
5: USBsuspend
USB Suspend
4: DetectSOF
Detect SOF Token
3: PortDMACmp
Port DMA Complete
2: SCSI
SCSI interrupt
1: RcvEP0SETUP
Receive EP0 SETUP Transaction
0: EPrIntStat
Epr Interrupt Status
BIT7 USB Resume
When Resume is present while the GoSuspend bit of the SystemCtrl register (09h) is being set, this bit becomes HIGH.
Clearing GoSuspend clears it.
BIT6 USB Reset
At USB reset, this bit becomes HIGH.
At the same time, the USB address register shown in “7.5.2.1 USB Address (USBAddress)” is cleared.
BIT5 USB Suspend
At USB Suspend, this bit becomes HIGH.
BIT4 Detect SOF Token
When the SOF Token is detected, this bit becomes HIGH.
BIT3 Port DMA Complete
This bit becomes HIGH when a port DMA transfer activated by the PortDMACtrl register (10h) ends.
It also becomes HIGH when the transfer is forced to terminate by writing “0” to the DTGO bit of the PortDMACtrl
register. In conditions of mode1:0=“00” of PortDMACtrl register, XINTU is set by this factor. In other modes,
XINTU is not set by this factor.
BIT2 SCSI Interrupt
When SCSI-related interrupt occurs, this bit becomes HIGH Detailed factors appear in MAINTS/SCSIINT1/SCSIINT2
register. This does not change when accessing this register.
BIT1 Receive EP0 SETUP Transaction
This bit becomes HIGH when the endpoint 0 completes the SETUP Stage normally.
The received data appears in the USBWindow_0 register (18h) - USBWindow_7 register (1Fh) following the setting of
the USBIndex register (17h) to 08h.
BIT0 EPr Interruput Status
This bit becomes HIGH when the interrupt status corresponding to each of the EPrIntStat register(01h) is a factor.
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