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| 型号： | S1R72105F00A000 |
| 元件分类： | 总线控制器 |
| 英文描述： | SCSI BUS CONTROLLER, PQFP100 |
| 封装： | 0.50 MM PITCH, PLASTIC, QFP15-100 |
| 文件页数： | 29/99页 |
| 文件大小： | 666K |
| 代理商： | S1R72105F00A000 |
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S1R72105 Technical Manual
Rev.1.0
EPSON
29
7.3.28
Main Interrupt Status SCSI (MAININTS)
R/W
When the IC causes an SCSI interruption to the CPU, the CPU identifies the interrupt status register responsible
for interruption by reading this register first.
Following the reading of this register, the CPU reads the interrupt status register corresponding to each bit and
performs appropriate interrupt processing by identifying the bit as a source of interruption. Then, it writes the
value read to the interrupt status register corresponding to each bit to clear the relevant bit.
If GOOD, SABT, or DTCMP bit is a source of interruption, the CPU writes the value read to clear the bits.
The register does not need to directly clear any other bits.
Address
Register Name
Bit Symbol
Description
20h
MAININTS
7: GOOD
SCSI COMMAND NORMAL COMPLETE
6: SABT
ABORTED SCSI COMMAND
5: EXEC
EXECUTING SCSI COMMAND
4: SCSI1
SCSI INTERRUPT STATUS 1
3: SCSI2
SCSI INTERRUPT STATUS 2
2: -
1: DTCMP
DMA TRANSFER COMPLETE
0: ASCMP
AUTO SEQUENCE COMPLETE
BIT7 SCSI COMMAND NORMAL COMPLETE
When the SCSI control command is terminated normally, this bit becomes HIGH.
BIT6 ABORTED SCSI COMMAND
When the control command is forced to terminate by issuing Abort command, this bit becomes HIGH.
BIT5 EXECUTING SCSI COMMAND
This bit is HIGH during execution of the SCSI control command. This bit does not cause an interruption to the CPU.
Even when it becomes HIGH no interruption is output. It is used to monitor the state of execution of the SCSI
control command.
BIT4 SCSI INTERRUPT STATUS 1
This bit becomes HIGH when there is any factor responsible for an interruption related to the SCSI interface shown in
the SCSIINT1 register.
BIT3 DMA INTERRUPT STATUS 2
This bit becomes HIGH when there is any factor responsible for interruption related to the SCSI interface shown in the
SCSIINT2 register.
BIT1 DMA TRANSFER COMPLETE
This bit becomes HIGH when DMA data transfer activated by the DMACTL register is completed.
It also becomes HIGH when the transfer is forced to terminate by writing “0” into the DTGO bit of the DMACTL
register.
After setting the DTGO bit of the DMACTL register, this bit becomes HIGH when a command is aborted by the
Abort_SCSI command or when a command in the course of execution is aborted by the ATN assertion, because DMA
terminates.
At times other than mode1:0=“00” of the PortDMACtrl register, XINTU is set by this factor. When mode1:0=“00”,
XINTS is not set by this factor.
* This bit has the same meaning as that of BIT(PortDMACmp) of MAINT(00h). It can be cleared by using any of the
registers.
BIT0 AUTO SEQUENCE COMPLETE
This bit becomes HIGH when AUTO1 or AUTO2 bit of the SCSIMODE0 register is set and the specified command is
terminated.
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