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参数资料
型号： S1R72105F00A000
元件分类： 总线控制器
英文描述： SCSI BUS CONTROLLER, PQFP100
封装： 0.50 MM PITCH, PLASTIC, QFP15-100
文件页数： 40/99页
文件大小： 666K
代理商： S1R72105F00A000
S1R72105 Technical Manual
Rev.1.0
EPSON
39
7.4
Detailed Description of Set Values of INTINDEX Register
7.4.1
Register Showing IntStatWindow_0,1 and IntEnbWindow_0,1 for Set Values of IntIndex
Register
IntIndex_n
IntStatWindow_n
IntEnbWindow_n
00h
EP0IntStat
EP0IntEnb
01h
EPaIntStat
EPaIntEnb
02h
EPbIntStat
EPbIntEnb
03h
EPcIntStat
EPcIntEnb
04h
Reserved
05h
Reserved
06h
Reserved
07h
Reserved
*n=0 or 1
7.4.2
EP {r} (r=0,a,b,c) Interrupt Status (EP {r} IntStat)
R/W
Shows the interrupt status of each interrupt status register endpoint displayed in IntStatWindow_0,1.
Following the reading of this register, the bit of a source of interruption is identified and it is cleared by writing
the value read after appropriate interrupt processing.
(The relevant bit is cleared by writing HIGH to each bit).
IntIndex_n: 0h to 3h
Address
Register Name
Bit Symbol
Description
02h,03h
EP0IntStat, EPaIntStat,
7: INtranACK
IN Transaction ACK
EPbIntStat, EPcIntStat,
6: OUTtranACK
OUT Transaction ACK
5: INtranErr
IN Transaction Error
4: OUTtranErr
OUT Transaction Error
3: INtranNAK
IN Transaction NAK
2: OUTtranNAK
OUT Transaction NAK
1: INtokenRcv
IN Token Received
0: OUTtokenRcv
OUT Token Received
BIT7 IN Transaction ACK
This bit becomes HIGH when ACK is received during IN Transaction.
BIT6 OUT Transaction Complete
This bit becomes HIGH when OUT Transaction is normally completed.
BIT5 IN Transaction Error
This bit becomes HIGH when IN Transaction ends abnormally.
Details can be obtained from the USBTransStatus register (0Bh).
BIT4 OUT Transaction Error
This bit becomes HIGH when OUT Transaction ends abnormally.
Details can be obtained from the USBTransStatus register (0Bh).
BIT3 IN Transaction NAK
This bit becomes HIGH when NAK is returned during IN Transaction.
BIT2 OUT Transaction NAK
This bit becomes HIGH when NAK is returned during OUT Transaction.
BIT1 IN Token Received
This bit becomes HIGH when BIT1 IN Token Received IN Token is received.
BIT0 OUT Token Received
This bit becomes HIGH when OUT Token is received.
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S1R72C05 制造商:EPSON 制造商全称:EPSON 功能描述:Support for control, bulk, interrupt, and isochronous transfers
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