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| 型号： | S1R72105F00A000 |
| 元件分类： | 总线控制器 |
| 英文描述： | SCSI BUS CONTROLLER, PQFP100 |
| 封装： | 0.50 MM PITCH, PLASTIC, QFP15-100 |
| 文件页数： | 4/99页 |
| 文件大小： | 666K |
| 代理商： | S1R72105F00A000 |
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S1R72105 Technical Manual
6
EPSON
Rev.1.0
6.
FUNCTIONAL DESCRIPTION
6.1
CPU Interface Circuit
This block can be interfaced to a general-purpose CPU. It generally controls the interface with the CPU.
When the XCS signal from the CPU is LOW, the block can access the internal register. It decodes the address
bus AD5 to AD0 to generate the address of the internal register. At this time, it generates the read/write strobe
signal from the XRD/XWR signal, transferring data between the internal register. A wait signal to the CPU is
not generated because of no-wait operation.
6.2
Internal Registers
Refer to the section of Register Functions as for the addresses of the internal registers and description of each
bit. The main functions of this block are as follows:
(1) It generates control signals to each block according to the address, write-data and write-strobe signals
generated by the CPU interface circuit.
(2) It stores the status signals from each block, and outputs data according to the address and read-strobe
signals sent from the CPU interface circuit.
6.3
Port Interface Circuit
This is a block controlling the transfer to and from the external DMA port. It has the following functions:
(1) It controls the linkage operation of each functional block according to the control signal and the
stop-operation signal sent from the DMA control circuit.
(2) It controls the transfer status of the external port according to PDREQ/XPDACK signals.
(3) It reads/writes data of the data bus PD15-0 of the port from/to FIFO in the SCSI-2 block. When transfer
is disabled in the full/empty state of SCSI_FIFO, transfer to and from the port is temporarily halted
according to the timing specified by the PDREQ/XPDACK signals.
(4) The port allows selection of bit width betweem 8 and 16.
(5) The port interface allows selection between the master and slave function (toward PDREQ/XPDACK/XPRD/XPWR
direction).
6.4
DMA Control Circuit
This block controls the transfer between the DMA port and FIFO in the SCSI block and FIFO in the USB block.
It has the following functions:
(1) It controls the linkage operation of each functional block according to the control signal from the internal
register and the information and stop-operation signals from each block.
(2) It stores the status of each of functional blocks when their linkage operation ends, reporting it to the
internal register at the specified timing.
6.5
SCSI-2 (3) Interface Circuit
This block generally controls the interfaces conforming to the SCSI-2 standard. It has the following functions:
(1) It automatically performs the SCSI protocol control on hardware.
(2) It has 16-staged off-set counter to control the off-set and transfer rate during synchronous transfer.
(3) In the command phase, it automatically distinguishes groups of commands received (in Target mode).
(4) It controls the automatic status/message transfer function. It supports the messages 00h/0Ah/0Bh.
(in Target mode).
(5) It allows SCSI-3 FAST20(20Mbps) transfer.
SCAM compatibility
In addition to conventional SCSI, this LSI has SCAM (SCSI Configured Auto Magnify)-compatible functions
as listed below:
These functions enable the device to operate as a SCAM Lv.1 drive.
(1) It monitors and recognizes the SCAM selection and causes an interruption.
(2) It responds to the selection response delay of 4ms or more, which enables distinction between SCAM and
ordinary selections.
(3) It can operate SCSI bus’s signal line directly because of its actual operation responding to the SCAM
selection and sending/receiving data.
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