参数资料
型号: S1R72105F00A000
元件分类: 总线控制器
英文描述: SCSI BUS CONTROLLER, PQFP100
封装: 0.50 MM PITCH, PLASTIC, QFP15-100
文件页数: 45/99页
文件大小: 666K
代理商: S1R72105F00A000
ii
EPSON
Rev.1.0
7.3.26 USB Window 6(USBWindow_6)
R/W ........................................................................28
7.3.27 USB Window 7(USBWindow_7)
R/W ........................................................................28
7.3.28 Main Interrupt Status SCSI (MAININTS)
R/W ...........................................................29
7.3.29 SCSI Interrupt Status 1 (SCSIINT1)
R/W ..................................................................30
7.3.30 SCSI Interrupt Status 2 (SCSIINT2)
R/W ..................................................................31
7.3.31 SCSI Mode Select0 (SCSIMODE0)
R/W ...................................................................32
7.3.32 SCSI Mode Select1 (SCSIMODE1)
R/W ...................................................................33
7.3.33 SCSI Control (SCSICTL)
R/W....................................................................................34
7.3.34 SCSI Data (SCSIDATA)
R/W .....................................................................................34
7.3.35 Synchronize Transfer Mode (SYNCMODE)
R/W.......................................................35
7.3.36 SCSI Own ID (OWNID)
R/W ......................................................................................35
7.3.37 Source/Destination ID (SDID)
R/W ............................................................................36
7.3.38 Selection Timeout Counter (SLTIME)
R/W ................................................................36
7.3.39 FIFO Control (FIFOCTL)
R/W ....................................................................................37
7.3.40 FIFO Data(FIFODATA)
R/W.......................................................................................37
7.3.41 Non DMA Transfer Size (NDMASIZ)
R/W .................................................................37
7.3.42 SCSI Command (COMMAND)
R/W...........................................................................38
7.3.43 Test(TEST)
R..............................................................................................................38
7.3.44 Revision Reg. (REVISION)
R.....................................................................................38
7.4
Detailed Description of Set Values of INTINDEX Register ......................................................39
7.4.1
Register Showing IntStatWindow_0,1 and IntEnbWindow_0,1 for Set Values of
IntIndex Register.........................................................................................................39
7.4.2
EP{r}(r=0,a,b,c) Interrupt Status(EP{r}IntStat)
R/W ..................................................39
7.4.3
EP{r}(r=0,a,b,c) Interrupt Enable(EP{r}IntEnb)
R/W .................................................40
7.5
Detailed Description of Set Values of USBIndex Register .......................................................41
7.5.1
List of Registers Showing USBWindow Register (8 bytes) Corresponding to
Set Values of USBIndex Register(17h) ......................................................................41
7.5.2
Description of Registers by Set Value of USBIndex ....................................................42
7.5.2.1 USB Address(USBAddress)
R/W ................................................................42
7.5.2.2 EP0 Config 1(EP0Config_1)
R/W................................................................42
7.5.2.3 EP0 In Transaction Control(EP0InControl)
R/W .........................................43
7.5.2.4 EP0 OUT Transaction Control(EP0OutControl)
R/W ..................................44
7.5.2.5 EP0 FIFO remain Counter(EP0FIFOremain)
R ..........................................45
7.5.2.6 EP0 FIFO for CPU(EP0FIFOforCPU)
R/W .................................................45
7.5.2.7 EP0 FIFO Control(EP0FIFOCtrl)
R/W .........................................................46
7.5.2.8
EP{r}(r=a,b,c) Config 0(EPrConfig_0)
R/W...............................................47
7.5.2.9
EP{r}(r=a,b,c) Config 1(EPrConfig_1)
R/W...............................................47
7.5.2.10 EP{r}(r=a,b,c) Control(EPrControl)
R/W ....................................................48
7.5.2.11 EP{r}(r=a,b,c) FIFO remain Counter(EPrFIFOremain)
R ..........................49
7.5.2.12 EPr FIFO for CPU(EPrFIFOforCPU)
R/W .................................................49
7.5.2.13 EPr FIFO Control(EPrFIFOCtrl)
R/W ........................................................50
7.5.2.14 EP0 SETUP[n](n=0,1,2,3,4,5,6,7) (EP0SETUP[n])
R ...............................50
7.5.2.15 Frame Number H(FrameNumber_H)
R.....................................................51
7.5.2.16 Frame NumberL(FrameNumber_L)
R .......................................................51
7.6
SCSI Control Commands .........................................................................................................52
7.6.1
Control Commands and Command Codes ..................................................................52
7.6.2
Description of Each Control Command........................................................................52
7.6.3
Command Execution and Change of State..................................................................60
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