30
S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127_064_032J_00_A1 May 21, 2004
Prelimin ary
access time is the delay from the falling edge of the OE# to valid data at the out-
put inputs (assuming the addresses have been stable for at least tACC–tOE time).
Page Mode Read
The device is capable of fast page mode read and is compatible with the page
mode Mask ROM read operation. This mode provides faster read access speed for
random locations within a page. Address bits Amax–A3 select an 8 word page,
and address bits A2–A0 select a specific word within that page. This is an asyn-
chronous operation with the microprocessor supplying the specific word location.
The random or initial page access is tACC or tCE and subsequent page read ac-
cesses (as long as the locations specified by the microprocessor falls within that
page) is equivalent to tPACC. Fast page mode accesses are obtained by keeping
Amax–A3 constant and changing A2–A0 to select the specific word within that
page.
Simultaneous Read/Write Operation
In addition to the conventional features (read, program, erase-suspend read, and
erase-suspend program), the device is capable of reading data from one bank of
memory while a program or erase operation is in progress in another bank of
memory (simultaneous operation). The bank can be selected by bank addresses
(PL127J: A22–A20, L064J: A21–A19, PL032J: A20–A18) with zero latency.
The simultaneous operation can execute multi-function mode in the same bank.
Table 2. Page Select
Word
A2
A1
A0
Word 0
0
Word 1
0
1
Word 2
0
1
0
Word 3
0
1
Word 4
1
0
Word 5
1
0
1
Word 6
1
0
Word 7
1
Table 3. Bank Select
Bank
PL127J: A22–A20
PL064J: A21–A19
PL032J: A20–A18
Bank A
000
Bank B
001, 010, 011
Bank C
100, 101, 110
Bank D
111