- 您现在的位置：买卖IC网 > PDF目录231009 > S71PL032J80BAW074 (SPANSION LLC) SPECIALTY MEMORY CIRCUIT, PBGA56 PDF资料下载
参数资料
| 型号： | S71PL032J80BAW074 |
| 厂商： | SPANSION LLC |
| 元件分类： | 存储器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA56 |
| 封装： | 7 X 9 MM, 1.20 MM HEIGHT, FBGA-56 |
| 文件页数： | 91/188页 |
| 文件大小： | 5078K |
| 代理商： | S71PL032J80BAW074 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页当前第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页第177页第178页第179页第180页第181页第182页第183页第184页第185页第186页第187页第188页
June 8, 2004 pSRAM_Type01_12_A0
pSRAM Type 1
120
Prelimin ary
freshed. The data in the remainder of the array will be lost. The PASR operation
mode is only available during standby time (ZZ# low) and once ZZ# is returned
high, the device resumes full array refresh. All future PASR cycles will use the
contents of the Mode Register that has been previously set. To change the ad-
dress space of the PASR mode, the Mode Register must be reset using the
previously defined procedures. For PASR to be activated, the register bit, A4Must
be set to a one (1) value, “PASR Enabled”. If this is the case, PASR will be acti-
vated 10 s after ZZ# is brought low. If the A4 register bit is set equal to zero
(0), PASR will not be activated.
Temperature Compensated Refresh (for 64Mb)
In this mode of operation, the internal refresh rate can be optimized for the op-
eration temperature used and this can then lower standby current. The DRAM
array in the PSRAM must be refreshed internally on a regular basis. At higher
temperatures, the DRAM cell must be refreshed more often than at lower tem-
peratures. By setting the temperature of operation in the Mode Register, this
refresh rate can be optimized to yield the lowest standby current at the given op-
erating temperature. There are four different temperature settings that can be
programmed in to the PSRAM. These are defined in Figure 86.
Deep Sleep Mode
In this mode of operation, the internal refresh is turned off and all data integrity
of the array is lost. Deep Sleep is entered by bringing ZZ# low with the A4 reg-
ister bit set to a zero (0), “Deep Sleep Enabled”. If this is the case, Deep Sleep
will be entered 10 s after ZZ# is brought low. The device will remain in this mode
as long as ZZ# remains low. If the A4 register bit is set equal to one (1), Deep
Sleep will not be activated.
Reduced Memory Size (for 32M and 16M)
In this mode of operation, the 32Mb PSRAM can be operated as a 8Mb or 16Mb
device. The mode and array size are determined by the settings in the VA register.
The VA register is set according to the following timings and the bit settings in
the table “Address Patterns for RMS”. The RMS mode is enabled at the time of ZZ
transitioning high and the mode remains active until the register is updated. To
return to the full 32Mb address space, the VA register must be reset using the
previously defined procedures. While operating in the RMS mode, the unselected
portion of the array may not be used.
Other Mode Register Settings (for 64M)
The Page Mode operation can also be enabled and disabled using the Mode Reg-
ister. Register bit A7 controls the operation of Page Mode and setting this bit to a
one (1), enables Page Mode. If the register bit A7 is set to a zero (0), Page Mode
operation is disabled.
相关PDF资料 |
PDF描述 |
|---|---|
| S71PL032JA0BAW074 | SPECIALTY MEMORY CIRCUIT, PBGA56 |
| S71PL032JA0BFW0F4 | SPECIALTY MEMORY CIRCUIT, PBGA56 |
| S29JL032H60TAI023 | 2M X 16 FLASH 3V PROM, 60 ns, PDSO48 |
| S29AL016D70BAI022 | 1M X 16 FLASH 3V PROM, 70 ns, PBGA48 |
| S29AL016D70TAN013 | 1M X 16 FLASH 3V PROM, 70 ns, PDSO48 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| S71PL032J80BAW0Z0 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:Based MCPs |
| S71PL032J80BAW0Z2 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:Based MCPs |
| S71PL032J80BAW0Z3 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:Based MCPs |
| S71PL032J80BAW9Z0 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:Based MCPs |
| S71PL032J80BAW9Z2 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:Based MCPs |
发布紧急采购，3分钟左右您将得到回复。