参数资料
型号: SI5315B-C-GMR
厂商: Silicon Laboratories Inc
文件页数: 47/54页
文件大小: 0K
描述: IC CLOCK MULT 8KHZ-125MHZ 36QFN
应用说明: SI5315/17 Crystal Selection AppNote
标准包装: 250
系列: DSPLL®
类型: 时钟/频率倍增器,抖动衰减器,多路复用器
PLL:
主要目的: 以太网,SONET/SDH/PDH,电信
输入: CML,CMOS,LVDS,LVPECL
输出: CML,CMOS,LVDS,LVPECL
电路数: 1
比率 - 输入:输出: 2:2
差分 - 输入:输出: 是/是
频率 - 最大: 125MHz
电源电压: 1.71 V ~ 3.63 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 36-VFQFN 裸露焊盘
供应商设备封装: 36-QFN(6x6)
包装: 带卷 (TR)
Si5315
Rev. 1.0
51
Table 22. PCB Land Pattern Dimensions
Dimension
Min
Max
e
0.50 BSC.
E5.42 REF.
D5.42 REF.
E2
4.00
4.20
D2
4.00
4.20
GE
4.53
GD
4.53
X
0.28
Y0.89 REF.
ZE
6.31
ZD
6.31
Notes (General):
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Notes (Solder Mask Design):
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 m minimum, all the way around the pad.
Notes (Stencil Design):
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the
center ground pad.
Notes (Card Assembly):
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for
Small Body Components.
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