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参数资料
| 型号： | SI5315B-C-GMR |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 9/54页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK MULT 8KHZ-125MHZ 36QFN |
| 应用说明： | SI5315/17 Crystal Selection AppNote |
| 标准包装： | 250 |
| 系列： | DSPLL® |
| 类型： | 时钟/频率倍增器，抖动衰减器，多路复用器 |
| PLL： | 无 |
| 主要目的： | 以太网，SONET/SDH/PDH，电信 |
| 输入： | CML，CMOS，LVDS，LVPECL |
| 输出： | CML，CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 125MHz |
| 电源电压： | 1.71 V ~ 3.63 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 36-VFQFN 裸露焊盘 |
| 供应商设备封装： | 36-QFN（6x6） |
| 包装： | 带卷 (TR) |
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Si5315
Rev. 1.0
17
4.2. PLL Performance
The Si5315 provides extremely low jitter generation, a well-controlled jitter transfer function, and high jitter
tolerance due to the high level of integration.
4.2.1. Jitter Generation
Jitter generation is defined as the amount of jitter produced at the output of the device with a jitter free input clock.
Generated jitter arises from sources within the VCO and other PLL components. Jitter generation is a function of
the PLL bandwidth setting. Higher loop bandwidth settings may result in lower jitter generation, but may result in
less attenuation of jitter that might be present on the input clock signal.
4.2.2. Jitter Transfer
Jitter transfer is defined as the ratio of output signal jitter to input signal jitter for a specified jitter frequency. The
jitter transfer characteristic determines the amount of input clock jitter that passes to the outputs. The DSPLL
technology used in the Si5315 provides tightly controlled jitter transfer curves because the PLL gain parameters
are determined largely by digital circuits which do not vary over supply voltage, process, and temperature. In a
system application, a well-controlled transfer curve minimizes the output clock jitter variation from board to board
and provides more consistent system level jitter performance.
The jitter transfer characteristic is a function of the loop bandwidth setting. Lower bandwidth settings result in more
jitter attenuation of the incoming clock, but may result in higher jitter generation. Figure 8 shows the jitter transfer
curve mask.
Figure 8. PLL Jitter Transfer Mask/Template
Jitter
Transfer
0 dB
BW
f
Jitter
Peaking
–20 dB/dec.
Jitter Out
Jitter In
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SI5315-C | 制造商:AUK 制造商全称:AUK corp 功能描述:IRED |
| SI5315-C(B) | 制造商:AUK 制造商全称:AUK corp 功能描述:IRED |
| SI5315-C_1 | 制造商:AUK 制造商全称:AUK corp 功能描述:IRED |
| SI5315-CB | 制造商:AUK 制造商全称:AUK corp 功能描述:IRED |
| SI5315-DS | 制造商:AUK 制造商全称:AUK corp 功能描述:High Speed IRED |
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