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参数资料
| 型号： | SI5325C-C-GM |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 8/62页 |
| 文件大小： | 0K |
| 描述： | IC UP-PROG CLK MULTIPLIER 36-QFN |
| 标准包装： | 490 |
| 系列： | DSPLL® |
| 类型： | 时钟乘法器 |
| PLL： | 是 |
| 输入： | 时钟 |
| 输出： | CML，CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 346MHz |
| 除法器/乘法器： | 是/是 |
| 电源电压： | 1.71 V ~ 3.63 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 36-VFQFN 裸露焊盘 |
| 供应商设备封装： | 36-QFN（6x6） |
| 包装： | 托盘 |
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Si5325
16
Rev. 0.5
2. Functional Description
The Si5325 is a low jitter, precision clock multiplier for
applications requiring clock multiplication without jitter
attenuation. The Si5325 accepts dual clock inputs
ranging from 10 to 710 MHz and generates two
synchronous clock outputs ranging from 2 kHz to
945 MHz and select frequencies to 1.4 GHz. The device
provides frequency translation across this operating
range. Independent dividers are available for each input
clock and output clock, so the Si5325 can accept input
clocks at different frequencies and it can generate
output clocks at different frequencies. The Si5325 input
clock frequency and clock multiplication ratio are
programmable through an I2C or SPI interface. Silicon
Laboratories
offers
a
PC-based
software
utility,
DSPLLsim, that can be used to determine the optimum
PLL divider settings for a given input frequency/clock
multiplication ratio combination that minimizes phase
noise and power consumption. This utility can be
downloaded from http://www.silabs.com/timing (click on
Documentation).
The Si5325 is based on Silicon Laboratories' third-
generation
DSPLL
technology,
which
provides
frequency synthesis in a highly integrated PLL solution
that eliminates the need for external VCXO and loop
filter components. The Si5325 PLL loop bandwidth is
digitally programmable and supports a range from
150kHz to 1.3MHz. The DSPLLsim software utility can
be used to calculate valid loop bandwidth settings for a
given input clock frequency/clock multiplication ratio.
In the case when the input clocks enter alarm
conditions, the PLL will freeze the DCO output
frequency near its last value to maintain operation with
an internal state close to the last valid operating state.
The Si5325 has two differential clock outputs. The
electrical format of each clock output is independently
programmable to support LVPECL, LVDS, CML, or
CMOS loads. If not required, the second clock output
can be powered down to minimize power consumption.
For system-level debugging, a bypass mode is available
which drives the output clock directly from the input
clock, bypassing the internal DSPLL. The device is
powered by a single 1.8, 2.5, or 3.3 V supply.
2.1. Further Documentation
Consult
the
Silicon
Laboratories
Any-Frequency
Precision Clock Family Reference Manual (FRM) for
detailed information about the Si5325. Additional design
support is available from Silicon Laboratories through
your distributor.
Silicon
Laboratories
has
developed
a
PC-based
software utility called DSPLLsim to simplify device
configuration, including frequency planning and loop
bandwidth selection. The FRM and this utility can be
downloaded from http://www.silabs.com/timing; click on
Documentation.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SI5325C-C-GMR | 功能描述:时钟发生器及支持产品 mP-Program Precision Clk Multiplier 2/2 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| SI5326 | 制造商:SILABS 制造商全称:SILABS 功能描述:ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR |
| Si5326A-B-GM | 功能描述:时钟合成器/抖动清除器 ANY-RATE CLK MULT JITTER ATTEN 2 OUTS RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| SI5326A-B-GMR | 制造商:Silicon Laboratories Inc 功能描述: |
| Si5326A-C-GM | 功能描述:时钟合成器/抖动清除器 ANY-RATE CLK MULT JITTER ATTEN 2 OUTS RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
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