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参数资料
| 型号： | SME5410MCZ-270 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 270 MHz, RISC PROCESSOR, XMA |
| 封装： | 130 X 100 MM, 45 MM HEIGHT MODULE |
| 文件页数： | 2/30页 |
| 文件大小： | 183K |
| 代理商： | SME5410MCZ-270 |
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SME5410MCZ-270
270 MHz CPU, 256 Kbyte E-cache, UPA, 66 MHz PCI
UltraSPARC-IIi CPU Module
July 1998
Sun Microsystems, Inc
Quick Signal Reference - Memory and XCVR Interface
Symbol
Type
Name and Function
MEM_WE_L
O
Memory Write Enable; active low
MEM_CAS_L[1:0]
O
Memory Column Address Strobe; active low
MEM_RAST_L[3:0]
O
Memory Row Address Strobe, Top; active low
MEM_RASB_L[3:0]
O
Memory Row Address Strobe, Bottom, active low
SYS
_DAT[63:0]
I/O
Memory / UPA64S data bus
MEM_ECC[7:0]
I/O
Memory ECC bits
MEM_ADR[12:0]
O
Memory Address bus, (row and column)
XCVR_OEA_L
O
Transceiver Output Enable A; active low
XCVR_OEB_L
O
Transceiver Output Enable B; active low
XCVR_SEL_L
O
Transceiver Select; Active low; picks high or low half of read data
XCVR_WR_CNTL[1:0]
O
Transceiver Write Control; controls clock enables on internal registers
XCVR_RD_CNTL[1:0]
O
Transceiver Read Control; controls clock enables on internal registers
XCVR_CLK[2:0]
O
Transceiver Clock; all data and control signals are registered by these clocks; multiple
outputs to minimize loading effects of six transceivers; should be parallel terminated to
GND on the motherboard
Quick Signal Reference - UPA64S Interface
Symbol
Type
Name and Function
UPA_S_REPLY[2:0]
O
UPA_S_REPLY; encoded command that indicates arrival of write data on
MEM_DATA[63:0], or command to drive MEM_DATA[63:0] with read data
UPA_P_REPLY[1:0]
I
UPA_P_REPLY; Encoded command that indicates consumption of prior write, or ability
to provide read data
UPA_ADR[28:0]
O
UPA_ADR; sends 2 cycle address packet to UPA64S slave, or provides internal state
debug information
UPA_ADR_VLD
O
UPA_ADR_VLD; asserted during rst cycle of two cycle address packet
SYS-DAT[63:0]
I/O
Memory/UPA64S Data bus
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