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SME5410MCZ-270
270 MHz CPU, 256 Kbyte E-cache, UPA, 66 MHz PCI
UltraSPARC-IIi CPU Module
July 1998
Sun Microsystems, Inc
SIGNAL DESCRIPTIONS
Quick Signal Reference - Clock Interface
Symbol
Type [1]
1. KEY: O – output; I – input; I/O – input or output; PECL – Positive Emitter-coupled Logic
Name and Function
UPA_CLK_POS,
UPA_CLK_NEG
O
PECL
Differential 3.3V PECL clock supplied to the UPA64S interface
PCI_REF_CLK
I
PCI reference clock; Should be 66 MHz. But this can be a 33 MHz PCI, if a 33 MHz PCI
interface is required
PCI_REF_CLK
I
PCI clock; always 66 MHz; doubled to 133 MHz for use in an internal PCI logic
Quick Signal Reference - JTAG/ Test /Temperature Interface (J0901)
Symbol
Type
Name and Function
TDO
O
IEEE 1149 test data output; tri-state signal driven only when the TAP controller is in the
shift-DR state
TDI
I
IEEE 1149 test data input; pin is internally pulled to logic one when not driven.
TCK
I
IEEE 1149 test clock input; pin must always be driven to logical 1 or logical 0 if not tied
to a clock source
TMS
I
IEEE 1149 test mode select input; internally pulled to logic 1 when not driven
TRST_L
I
IEEE 1149 test reset input (active low); internally pulled to logical 1 when not driven
TEMP_SENSE[1:0]
O
Temperature sensing thermistor terminals on the module
MFG_L
I
For manufacturing test use, no connect
Quick Signal Reference - Initialization Interface
Symbol
Type
Name and Function
PO_RST_L
I
For non power-on resets; for debug; asynchronous assertion and de-assertion; active
low
S_DATA
I
Serial frequency-setting data for MC12430 module clock synthesizer
S_CLK
I
Data clock for module clock synthesizer
S_LOAD
I
Serial load mode pin for clock synthesizer
X_RESET_L
I
Driven to signal XIR traps; for debug; behaves as a non-maskable interrupt;
asynchronous assertion and de-assertion; active low
SYS_RESET_L
I
Driven for POR (power-on) resets; asynchronous assertion and de-assertion; active low
PCI_RESET_L
O
Resets PCI subsystem; asynchronous assertion and monotonic deassertion; also used
for UPA64S reset
PCI_CLKSEL[1:0]
O
Selects PCI clock frequency generated on the system board
VID[4:0]
O
V
dd_CORE voltage digital programming