参数资料
型号: SME5410MCZ-270
元件分类: 微控制器/微处理器
英文描述: 64-BIT, 270 MHz, RISC PROCESSOR, XMA
封装: 130 X 100 MM, 45 MM HEIGHT MODULE
文件页数: 3/30页
文件大小: 183K
代理商: SME5410MCZ-270
11
270 MHz CPU, 256 Kbyte E-cache, UPA, 66 MHz PCI
UltraSPARC-IIi CPU Module
SME5410MCZ-270
July 1998
Sun Microsystems, Inc
CLOCK DISTRIBUTION
A raw clock signal is generated within the module using a Motorola high frequency PLL clock generator
(MC12430) with a 16MHz series resonant crystal. The MC12430 provides a serial and parallel interface for
conguring the frequency synthesis. The parallel interface pins are hardwired on the module but the serial
interface signals S_LOAD, S_DATA, and S_CLOCK are brought out to the Memory/UPA64S external connec-
tor to allow clock conguration from the motherboard.
The raw clock from this clock generator is divided down in a clock divider (MC100LVEL39) to produce the
processor SRAM and UPA64S clock signals. Only the differential Low Voltage Positive ECL (LVPECL)
UPA64S clock signal (at 1/3 of the CPU clock frequency) is output to the 180-pin Memory/UPA64S external
connector.
An clock buffer (MCLVE210) distributes the CPU and SRAM clocks.
The JTAG TCK signal enters the module via the 120-pin PCI/JTAG connector (J0901) and connects to the
SRAMs and the UltraSPARC-IIi processor.
The incoming motherboard PCI_CLK and the PCI_REF_CLK signals also arrive at the PCI/JTAG/Tempera-
ture sense interface connector and travel to the UltraSPARC-IIi.
The UltraSPARC-IIi CPU module can select motherboard PCI clock generator frequency values to be in
either the 66 MHz/33 MHz or the 60 MHz/30 MHz sets. The PCI/JTAG connector (J0901) signals
(PCI_CLKSEL0 and PCI_CLKSEL1) provide frequency-encoding bits that conform to IC Works’ CPU/PCI
System Clock Generator (Part Number W48C60-422) specication. The table "PCI Frequency Selection."
shows this encoding.
.
TABLE 1: PCI Frequency Selection
PCI_CLKSEL0
PCI_CLKSEL1
PCI Clock Rate
0
1
30/60 MHz
1
0
33/66 MHz
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