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参数资料
| 型号： | SPAK56F807VF80 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 16-BIT, 80 MHz, OTHER DSP, PBGA160 |
| 封装： | MOLD ARRAY PROCESS, BGA-160 |
| 文件页数： | 12/48页 |
| 文件大小： | 853K |
| 代理商： | SPAK56F807VF80 |
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2
DSP56F807 Preliminary Technical Data
MOTOROLA
Part 1 Overview
1.1 DSP56F807 Features
1.1.1
Digital Signal Processing Core
Efficient 16-bit DSP56800 family DSP engine with dual Harvard architecture
As many as 40 Million Instructions Per Second (MIPS) at 80 MHz core frequency
Single-cycle 16
× 16-bit parallel Multiplier-Accumulator (MAC)
Two 36-bit accumulators including extension bits
16-bit bidirectional barrel shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three internal address buses and one external address bus
Four internal data buses and one external data bus
Instruction set supports both DSP and controller functions
Controller style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/OnCE debug programming interface
1.1.2
Memory
Harvard architecture permits as many as three simultaneous accesses to program and data memory
On-chip memory including a low-cost, high-volume flash solution
—60K
× 16-bit words of Program Flash
—2K
× 16-bit words of Program RAM
—8K
× 16-bit words of Data Flash
—4K
× 16-bit words of Data RAM
—2K
× 16-bit words of Boot Flash
Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states
— As much as 64K
× 16 bits of data memory
— As much as 64K
× 16 bits of program memory
1.1.3
Peripheral Circuits for DSP56F807
Two Pulse Width Modulator modules each with six PWM outputs, three Current Sense inputs, and
four Fault inputs, fault tolerant design with deadtime insertion, supports both center and edge
aligned modes
Four 12-bit, Analog-to-Digital Converters (ADCs), which support four simultaneous conversions
with quad, 4-pin multiplexed inputs; ADC and PWM modules can be synchronized
Two Quadrature Decoders each with four inputs or two additional Quad Timers
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