参数资料
型号: SST26WF032-80-4I-QAE
厂商: SILICON STORAGE TECHNOLOGY INC
元件分类: PROM
英文描述: 32M X 1 SPI BUS SERIAL EEPROM, PDSO8
封装: 6 X 5 MM, ROHS COMPLIANT, WSON-8
文件页数: 33/36页
文件大小: 1339K
代理商: SST26WF032-80-4I-QAE
2010 Silicon Storage Technology, Inc.
S71409-01-000
01/10
6
1.8V Serial Quad I/O (SQI) Flash Memory
SST26WF032
Advance Information
Device Operation
The SST26WF032 supports both Serial Peripheral Interface (SPI) bus protocol and the new 4-bit mul-
tiplexed Serial Quad I/O (SQI) bus protocol. To provide backward compatibility to traditional SPI Serial
Flash devices, the device’s initial state after a power-on reset is SPI bus protocol supporting only
Read, High Speed Read, and JEDEC-ID Read instructions. A command instruction configures the
device to Serial Quad I/O bus protocol. The dataflow in this bus protocol is controlled with four multi-
plexed I/O signals, a chip enable (CE#), and serial clock (SCK).
SQI Flash Memory protocol supports both Mode 0 (0,0) and Mode 3 (1,1) bus operations. The differ-
ence between the two modes, as shown in Figures 4 and 5, is the state of the SCK signal when the
bus master is in Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0
and SCK signal is high for Mode 3. For both modes, the Serial Data I/O (SIO[3:0]) is sampled at the ris-
ing edge of the SCK clock signal for input, and driven after the falling edge of the SCK clock signal for
output. The traditional SPI protocol uses separate input (SI) and output (SO) data signals as shown in
Figure 4. The SST26WF032 uses four multiplexed signals, SIO[3:0], for both data in and data out, as
shown in Figure 5. This quadruples the traditional bus transfer speed at the same clock frequency,
without the need for more pins on the package.
Figure 4: SPI Protocol (Traditional 25 Serial SPI Device)
Figure 5: SQI Serial Quad I/O Protocol
1409 F03.0
MODE 3
SCK
SI
SO
CE#
MODE 3
DON'T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MODE 0
HIGH IMPEDANCE
MSB
1409 F04.1
MODE 3
CLK
SIO(3:0)
CE#
MODE 3
C1
C0
A5
A4
A3
A2
A1
A0
H0
L0
H1
L1
H2
L2
H3
L3
MODE 0
MSB
X = Don’t Care or High Impediance
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