参数资料
型号: SST26WF032-80-4I-QAE
厂商: SILICON STORAGE TECHNOLOGY INC
元件分类: PROM
英文描述: 32M X 1 SPI BUS SERIAL EEPROM, PDSO8
封装: 6 X 5 MM, ROHS COMPLIANT, WSON-8
文件页数: 6/36页
文件大小: 1339K
代理商: SST26WF032-80-4I-QAE
2010 Silicon Storage Technology, Inc.
S71409-01-000
01/10
14
1.8V Serial Quad I/O (SQI) Flash Memory
SST26WF032
Advance Information
Read (25 MHz)
The Read instruction, 03H, is supported in SPI bus protocol only with clock frequencies up to 25 MHz.
This command is not supported in SQI bus protocol. The device outputs the data starting from the
specified address location, then continuously streams the data output through all addresses until ter-
minated by a low-to-high transition on CE#. The internal address pointer will automatically increment
until the highest memory address is reached. Once the highest memory address is reached, the
address pointer will automatically return to the beginning (wrap-around) of the address space.
Initiate the Read instruction by executing an 8-bit command, 03H, followed by address bits A23:A0.
CE# must remain active low for the duration of the Read cycle. SIO2 and SIO3 must be driven VIH for
the duration of the Read cycle. See Figure 8 for Read Sequence.
Figure 8: Read Sequence (SPI)
Enable Quad I/O (EQIO)
The Enable Quad I/O (EQIO) instruction, 38H, enables the flash device for SQI bus operation. upon
completion of the instruction, all instructions thereafter will be 4-bit multiplexed input/output until a
power cycle or a “Reset Quad I/O instruction” is executed. See Figure 9.
Figure 9: Enable Quad I/O Sequence
1409 F29.0
CE#
SO
SI
SCK
ADD.
01 2 3 4 5 6 7 8
ADD.
03
HIGH IMPEDANCE
15 16
23 24
31 32
39 40
70
47 48
55 56
63 64
N+2
N+3
N+4
N
N+1
DOUT
MSB
MODE 0
MODE 3
DOUT
Note: SIO2 and SIO3 must be driven VIH
1409 F43.0
MODE 3
0
1
SCK
SIO0
CE#
MODE 0
234567
38
SIO[3:1]
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