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参数资料
| 型号： | SST49LF003B-33-4C-NH |
| 厂商： | SILICON STORAGE TECHNOLOGY INC |
| 元件分类： | PROM |
| 英文描述： | 384K X 8 FLASH 3V PROM, 11 ns, PQCC32 |
| 封装： | PLASTIC, MS-016AE, LCC-32 |
| 文件页数： | 6/43页 |
| 文件大小： | 500K |
| 代理商： | SST49LF003B-33-4C-NH |
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14
Data Sheet
2 Mbit / 3 Mbit / 4 Mbit LPC Firmware Flash
SST49LF002B / SST49LF003B / SST49LF004B
2005 Silicon Storage Technology, Inc.
S71232-05-000
1/05
Firmware Memory Read Cycle
FIGURE 6: FIRMWARE MEMORY READ CYCLE WAVEFORM
TABLE
5: FIRMWARE MEMORY READ CYCLE FIELD DEFINITIONS
Clock
Cycle
Field
Name
Field Contents
LAD[3:0]1
1. Field contents are valid on the rising edge of the present clock cycle.
LAD[3:0]
Direction
Comments
1
START
1101
IN
LFRAME# must be active (low) for the device to respond.
Only the last field latched before LFRAME# transitions high
will be recognized. The START field contents (1101b) indi-
cate a Firmware Memory Read cycle.
2
IDSEL
0000 to 1111
IN
Indicates which SST49LF00xB device should respond. If the
IDSEL (ID select) field matches the value of ID[3:0], the device
will respond to the LPC bus cycle.
3-9
MADDR
YYYY
IN
These seven clock cycles make up the 28-bit memory
address. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
10
MSIZE
0000 (1 Byte)
IN
The MSIZE field indicates how many bytes will be trans-
ferred during multi-byte operations. The SST49LF00xB only
supports single-byte operation. MSIZE=0000b
11
TAR0
1111
IN then Float
In this clock cycle, the master has driven the bus to all ‘1’s
and then floats the bus, prior to the next clock cycle. This is
the first part of the bus “turnaround cycle.”
12
TAR1
1111 (float)
Float then
OUT
The SST49LF00xB takes control of the bus during this
cycle.
13
RSYNC
0000 (READY)
OUT
During this clock cycle, the device generates a “ready sync”
(RSYNC) indicating that the device has received the input
data.
14
DATA
ZZZZ
OUT
ZZZZ is the least-significant nibble of the data byte.
15
DATA
ZZZZ
OUT
ZZZZ is the most-significant nibble of the data byte.
16
TAR0
1111
OUT then
Float
In this clock cycle, the SST49LF00xB drives the bus to all
ones and then floats the bus prior to the next clock cycle.
This is the first part of the bus “turnaround cycle.”
17
TAR1
1111 (float)
Float then IN
The host resumes control of the bus during this cycle.
T5.1 1232
1232 F03.0
LFRAME#
LAD[3:0]
1101b
0000b
A[23:20] A[19:16]
A[3:0]
A[7:4]
A[11:8]
A[15:12]
MADDR
Start
IDSEL
MSIZE
LCLK
A[27:24]
0000b
RSYNC
TAR1
TAR0
TAR
D[7:4]
Tri-State
D[3:0]
0000b
1111b
DATA
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相关代理商/技术参数 |
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| SST49LF004A | 制造商:SST 制造商全称:Silicon Storage Technology, Inc 功能描述:2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub |
| SST49LF004A-33-4C-NH | 制造商:Silicon Storage Technology (SST) 功能描述:NOR Flash, 512K x 8, 32 Pin, Plastic, PLCC |
| SST49LF004A-33-4C-WH | 制造商:SST 制造商全称:Silicon Storage Technology, Inc 功能描述:2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub |
| SST49LF004B | 制造商:SST 制造商全称:Silicon Storage Technology, Inc 功能描述:4 Mbit Firmware Hub |
| SST49LF004B_06 | 制造商:SST 制造商全称:Silicon Storage Technology, Inc 功能描述:4 Mbit Firmware Hub |
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